CY7C1338B-100AC Cypress Semiconductor Corp, CY7C1338B-100AC Datasheet
CY7C1338B-100AC
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CY7C1338B-100AC Summary of contents
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... Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-05143 Rev. ** Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap- tures the first address in a burst and increments the address automatically for the rest of the burst access ...
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... Pin Configurations DDQ V SSQ BYTE2 SSQ V DDQ DDQ V SSQ BYTE3 SSQ V DDQ Document #: 38-05143 Rev. ** 100-Pin TQFP CY7C1338B CY7C1338B DDQ V 76 SSQ BYTE1 SSQ V 70 DDQ DDQ 60 V SSQ BYTE0 SSQ 54 V DDQ Page ...
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... BWE and BW CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CE Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE 1 Synchronous and CE 3 Document #: 38-05143 Rev. ** 119-Ball BGA CY7C1338B (128K x 32 ADSP DDQ ADSC ...
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... Maximum access delay from the clock rise ( 7.5 ns (117-MHz device). CDV The CY7C1338B supports secondary cache in systems utiliz- ing either a linear or interleaved burst sequence. The inter- leaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
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... OE. Burst Sequences The CY7C1338B provides an on-chip 2-bit wraparound burst counter inside the SRAM. The burst counter is fed by A and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence ...
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... Document #: 38-05143 Rev ADSP ADSC CY7C1338B ADV WE OE CLK L-H High L-H High L-H High L-H High L-H High High L L-H High L L L-H High L L-H High L L-H High L-H High L L-H High L L-H D Writes may occur only on subsequent clocks [3:0]. Page ...
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... A Document #: 38-05143 Rev BWE Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Ambient Range Temperature Com’ + 0.5V Ind’l – + 0.5V DD CY7C1338B [ DDQ 3.135V to 3.6V 2.375V Page ...
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... IN IN DDQ inputs static Max Device Deselected – 0. 0.3V, IN DDQ inputs switching MAX Max Device Deselected – 0. 0.3V inputs static CY7C1338B Min. Max. 2.4 2.0 0.4 0.7 2 0.3V 1 0.3V –0.3 0.8 –0.3 0 –30 5 –5 30 –5 5 –300 8.5-ns cycle, 117 MHz ...
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... MHz 5.0V DD R1=317 3.3V OUTPUT R2=351 5 pF INCLUDING JIG AND SCOPE (b) [9] Description [10, 12] [10, 12] (max) is less than t (min). CLZ CY7C1338B Max. 5.0 8.0 ALL INPUT PULSES 3.0V 90% 90% 10% GND 3.0 ns -117 -100 Min. Max. Min. Max. 8.5 10 3.0 4.0 3.0 4 ...
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... WDx stands for Write Data to Address X. Document #: 38-05143 Rev. ** Burst Write ADSP ignored with CE CL WD2 masks ADSP UNDEFINED = DON’T CARE , and GW to define a write cycle (see Write Cycle Descriptions table). CY7C1338B Pipelined Write Unselected inactive 1 ADSC initiated write WD3 Unselected with CE 2 High Page ...
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... Note: 15. RDx stands for Read Data from Address X. Document #: 38-05143 Rev. ** Burst Read ADSP ignored with Suspend Burst ADH RD2 DOH CLZ = DON’T CARE = UNDEFINED CY7C1338B Unselected Pipelined Read inactive 1 ADSC initiated read RD3 masks ADSP Unselected with CHZ 2 Page ...
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... ADVH ADVS t WES ADSP ignored with CE HIGH Q(B) (B+2) (B+1) (B+3) , and GW to define a write cycle (see Write Cycle Descriptions table). [1:0] and CE . All chip selects need to be active in order to select 2 3 CY7C1338B ADH t CEH t CEH t WEH t EOHZ D(C) (C+1) (C+2) ...
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... E t ADH t WES ADSP ignored with CE HIGH 1 Q(D) , and GW to define a write cycle (see Write Cycle Descriptions table). [1:0] and CE . All chip selects need to be active in order to select DON’T CARE = UNDEFINED CY7C1338B CEH t WEH D (E) D (F) D (H) D (G) D(C) t DOH t ...
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... Timing Diagrams (continued) OE Switching Waveforms OE t EOHZ three-state I/Os Document #: 38-05143 Rev EOV t EOLZ CY7C1338B Page ...
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... LOW CE 2 HIGH I/Os Notes: 16. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 17. I/Os are in three-state when exiting ZZ “sleep” mode. Document #: 38-05143 Rev ZZS I (active CCZZ Three-state CY7C1338B t ZZREC Page ...
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... Ordering Information Speed (MHz) Ordering Code 117 CY7C1338B-117AC CY7C1338B-117BGC 100 CY7C1338B-100AC CY7C1338B-100BGC CY7C1338B-100AI CY7C1338B-100BGI Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05143 Rev. ** Package Name Package Type A101 100-Lead Thin Quad Flat Pack BG119 119-Ball BGA A101 100-Lead Thin Quad Flat Pack ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead FBGA ( 2.4 mm) BG119 CY7C1338B 51-85115 Page ...
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... Document Title: CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Document Number: 38-05143 Issue REV. ECN NO. Date ** 109887 09/15/01 Document #: 38-05143 Rev. ** Orig. of Change SZV Change from Spec number 38-00939 to 38-05143 CY7C1338B Description of Change Page ...