MT47H32M16BN-25:D TR Micron Technology Inc, MT47H32M16BN-25:D TR Datasheet - Page 75
![IC DDR2 SDRAM 512MBIT 84FBGA](/photos/7/23/72318/mfg557-84-fbga_sml.jpg)
MT47H32M16BN-25:D TR
Manufacturer Part Number
MT47H32M16BN-25:D TR
Description
IC DDR2 SDRAM 512MBIT 84FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H128M4BT-37EA_TR.pdf
(129 pages)
Specifications of MT47H32M16BN-25:D TR
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (32Mx16)
Speed
2.5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
84-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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CAS Latency (CL)
Figure 35: CL
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. O 7/09 EN
Notes:
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 34 (page 72). CL is
the delay, in clock cycles, between the registration of a READ command and the availa-
bility of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as an unknown operation otherwise incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea-
ture allows the READ command to be issued prior to
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
further detail in Posted CAS Additive Latency (AL) (page 78).
Examples of CL = 3 and CL = 4 are shown in Figure 35; both assume AL = 0. If a READ
command is registered at clock edge n, and the CL is m clocks, the data will be available
nominally coincident with clock edge n + m (this assumes AL = 0).
DQS, DQS#
DQS, DQS#
Command
Command
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal
CK#
CK#
DQ
DQ
CK
CK
READ
READ
T0
T0
NOP
NOP
T1
T1
CL = 3 (AL = 0)
t
AC,
75
t
DQSCK, and
CL = 4 (AL = 0)
NOP
NOP
T2
T2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSQ.
512Mb: x4, x8, x16 DDR2 SDRAM
NOP
NOP
T3
T3
DO
n
t
RCD (MIN) by delaying the
n + 1
DO
NOP
NOP
T4
T4
Mode Register (MR)
n + 2
DO
DO
n
©2004 Micron Technology, Inc. All rights reserved.
Transitioning data
n + 1
n + 3
DO
DO
NOP
NOP
T5
T5
n + 2
DO
n + 3
DO
NOP
NOP
Don’t care
T6
T6
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