MT46V64M8TG-6T:D Micron Technology Inc, MT46V64M8TG-6T:D Datasheet - Page 68
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MT46V64M8TG-6T:D
Manufacturer Part Number
MT46V64M8TG-6T:D
Description
IC DDR SDRAM 512MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V64M8TG-6T:D
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (64M x 8)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
175mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1039-2
MT46V64M8TG-6T:D TR
MT46V64M8TG-6T:D TR
Figure 33:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Command
Command
Command
Address
Address
Address
READ-to-PRECHARGE
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
Notes:
Bank a,
Bank a,
Bank a,
READ
READ
READ
Col n
Col n
Col n
T0
T0
T0
1. Provided
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
7. An ACTIVE command to the same bank is only allowed if
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
assumed that
CL = 2
t
RAS (MIN) is met, a READ command with auto precharge enabled would cause a
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
RAS (MIN) is met.
CL = 3
t
AC,
(a or all)
(a or all)
(a or all)
Bank a,
Bank a,
Bank a,
T2
PRE
PRE
PRE
T2
T2
t
DQSCK, and
68
DO
n
T2n
T2n
DO
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
T3
NOP
T3
NOP
t
DQSQ.
DO
n
t RP
t RP
t RP
T3n
T3n
T3n
512Mb: x4, x8, x16 DDR SDRAM
Transitioning Data
T4
NOP
T4
T4
NOP
NOP
t
RC (MIN) is met.
T4n
©2000 Micron Technology, Inc. All rights reserved.
Bank a,
Bank a,
Bank a,
T5
T5
T5
Row
ACT
ACT
Row
ACT
Row
Don’t Care
Operations