MT46V64M8TG-6T:D Micron Technology Inc, MT46V64M8TG-6T:D Datasheet - Page 54
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MT46V64M8TG-6T:D
Manufacturer Part Number
MT46V64M8TG-6T:D
Description
IC DDR SDRAM 512MBIT 6NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V32M16P-5BF_TR.pdf
(91 pages)
Specifications of MT46V64M8TG-6T:D
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
512M (64M x 8)
Speed
6ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx8
Density
512Mb
Address Bus
15b
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
175mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1039-2
MT46V64M8TG-6T:D TR
MT46V64M8TG-6T:D TR
Figure 22:
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. N; Core DDR Rev. B 2/09 EN
Command
BA0, BA1
Address
V
V
DQS
DD
V
CK#
CKE
A10
V
DM
DQ
CK
TT
REF
DD
Q
1
t VTD 1
INITIALIZATION Timing Diagram
Notes:
LVCMOS
LOW level
Power-up: V
T = 200µs
1. V
2. Although not required by the Micron device, JEDEC specifies issuing another LMR command
3. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LMR com-
4.
5. While programming the operating parameters, reset the DLL with A8 = 1.
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V
even if V
the V
specified range.
(A8 = 0) prior to activating any bank. If another LMR command is issued, the same, previ-
ously issued operating parameters must be used.
mand at Ta0.
t
DESELECTs are allowed), and 200 cycles of CK are required before a READ command can be
issued.
MRD is required before any command can be applied (during MRD time only NOPs or
DD
TT
TT
t IS t IH
t IS
and CK stable
NOP
, and V
T0
is not applied directly to the device; however,
High-Z
High-Z
TT
t IH
t CH
t CK
supply and the input pin. Once initialized, V
DD
REF
/V
t CL
All banks
DD
t IS t IH
≤ V
PRE
T1
Q are 0V, provided a minimum of 42Ω of series resistance is used between
DD
+ 0.3V. Alternatively, V
t RP
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Load extended
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mode register
t IS t IH
t IS t IH
t IS t IH
BA0 = 1
BA1 = 0
Code
Code
LMR
Ta0
54
t MRD
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Load mode
register5
Code 3
BA0 = 0
BA1 = 0
Code
LMR
Tb0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t MRD
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may be 1.35V maximum during power-up,
All banks
t IS t IH
512Mb: x4, x8, x16 DDR SDRAM
PRE
Tc0
t
VTD ≥ 0 to avoid device latch-up. V
REF
t RP
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must always be powered within the
200 cycles of CK4
Td0
AR
Indicates A Break in
Time Scale
©2000 Micron Technology, Inc. All rights reserved.
t RFC
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Te0
AR
t RFC
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ACT 2
Don’t Care
Tf0
BA
RA
RA
DD
Q,