UPD44324365F5-E40-EQ2 Renesas Electronics America, UPD44324365F5-E40-EQ2 Datasheet - Page 8

• Manufacturer Part Number: UPD44324365F5-E40-EQ2
• Description: SRAM QDRII 36MBIT 165-PBGA
• Manufacturer: Renesas Electronics America

Specifications of UPD44324365F5-E40-EQ2

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 36M (1M x 36)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Identification
8
A
D0 to Dxx
Q0 to Qxx
LD#
R, W#
BWx#
NWx#
K, K#
C, C#
Symbol
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). These
inputs are ignored when device is deselected, i.e., NOP (LD# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K#
during WRITE operations. See Pin Configurations for ball site location of individual signals.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges
if C and C# are tied HIGH. Data is output in synchronization with C and C# (or K and K#), depending on the
LD# and R, W# command. See Pin Configurations for ball site location of individual signals.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus
activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W#
is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times
around the rising edge of K.
Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin
Configurations for signal to data relationships.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
C# is used as the output timing reference for first output data. The rising edge of C is used as the output
reference for second output data. Ideally, #C is 180 degrees out of phase with C. When use of K and K# as the
reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and
C# are fixed to HIGH (i.e. toggle of C and C#)
See Byte Write Operation for relation between BWx#, NWx# and Dxx.
x8 device uses D0 to D7.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
x8 device uses Q0 to Q7.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
x8 device uses NW0#, NW1#.
x9 device uses BW0#.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
μ
PD44324085-A, 44324095-A, 44324185-A, 44324365-A
Data Sheet M19873EJ1V0DS
Description
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