LH28F160BJHE-TTL90 Sharp Microelectronics, LH28F160BJHE-TTL90 Datasheet - Page 18

• Manufacturer Part Number: LH28F160BJHE-TTL90
• Description: IC FLASH 16MBIT 90NS 48TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F160BJHE-TTL90

• Rohs Status: RoHS non-compliant
• Format - Memory: FLASH
• Memory Type: Boot Block FLASH
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Other names: 425-1824; LH28F160BJHE-BTL90; LHF16J04

4.10 Set Block and Permanent Lock-Bit
A flexible block locking and unlocking scheme is enabled
via a combination of block lock-bits, a permanent lock-bit
and WP# pin. The block lock-bits and WP# pin gates
program and erase operations while the permanent lock-bit
gates block-lock bit modification. With the permanent
lock-bit not set, individual block lock-bits can be set using
the Set Block Lock-Bit command. The Set Permanent
Lock-Bit command, sets the permanent lock-bit. After the
permanent lock-bit is set, block lock-bits and locked block
contents cannot altered. See Table 5 for a summary of
hardware and software write protection options.
Set block lock-bit and permanent lock-bit are executed by
a two-cycle command sequence. The set block or
permanent lock-bit setup along with appropriate block or
device address is written followed by either the set block
lock-bit confirm (and an address within the block to be
locked) or the set permanent lock-bit confirm (and any
device address). The WSM then controls the set lock-bit
algorithm. After the sequence is written, the device
automatically outputs status register data when read (see
Figure 10). The CPU can detect the completion of the set
lock-bit event by analyzing the RY/BY# pin output or
status register bit SR.7.
When the set lock-bit operation is complete, status register
bit SR.4 should be checked. If an error is detected, the
status register should be cleared. The CUI will remain in
read status register mode until a new command is issued.
This two-step sequence of set-up followed by execution
ensures that lock-bits are not accidentally set. An invalid
Set Block or Permanent Lock-Bit command will result in
status register bits SR.4 and SR.5 being set to "1". Also,
reliable operations occur only when V
V
lock-bit contents are protected against alteration.
A successful set block lock-bit operation requires that the
permanent lock-bit be cleared. If it is attempted with the
permanent lock-bit set, SR.1 and SR.4 will be set to "1"
and the operation will fail.
sharp
CCW
=V
Commands
CCWH1/2
. In the absence of this high voltage,
CC
=2.7V-3.6V and
LHF16J04
4.11 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the Clear
Block Lock-Bits command. With the permanent lock-bit
not set, block lock-bits can be cleared using only the Clear
Block Lock-Bits command. If the permanent lock-bit is
set, block lock-bits cannot cleared. See Table 5 for a
summary of hardware and software write protection
options.
Clear block lock-bits operation is executed by a two-cycle
command sequence. A clear block lock-bits setup is first
written. After the command is written, the device
automatically outputs status register data when read (see
Figure 11). The CPU can detect completion of the clear
block lock-bits event by analyzing the RY/BY# Pin output
or status register bit SR.7.
When the operation is complete, status register bit SR.5
should be checked. If a clear block lock-bit error is
detected, the status register should be cleared. The CUI
will remain in read status register mode until another
command is issued.
This two-step sequence of set-up followed by execution
ensures that block lock-bits are not accidentally cleared.
An invalid Clear Block Lock-Bits command sequence will
result in status register bits SR.4 and SR.5 being set to "1".
Also, a reliable clear block lock-bits operation can only
occur when V
clear block lock-bits operation is attempted while
V
absence of this high voltage, the block lock-bits content
are protected against alteration. A successful clear block
lock-bits operation requires that the permanent lock-bit is
not set. If it is attempted with the permanent lock-bit set,
SR.1 and SR.5 will be set to "1" and the operation will
fail.
If a clear block lock-bits operation is aborted due to V
or V
transition,
undetermined state. A repeat of clear block lock-bits is
required to initialize block lock-bit contents to known
values. Once the permanent lock-bit is set, it cannot be
cleared.
CCW
CC
≤V
transitioning out of valid range or RP# active
CCWLK
block
CC
, SR.3 and SR.5 will be set to "1". In the
=2.7V-3.6V and V
lock-bit
values
CCW
are
=V
CCWH1/2
left
Rev. 1.26
in
. If a
CCW
15
an