IDT71321SA55J IDT, Integrated Device Technology Inc, IDT71321SA55J Datasheet - Page 8

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IDT71321SA55J

Manufacturer Part Number
IDT71321SA55J
Description
IC SRAM 16KBIT 55NS 52PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71321SA55J

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
16K (2K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
71321SA55J

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CURRENT
Timing Waveform of Read Cycle No. 1, Either Side
NOTES:
1. R/W = V
2. t
3. Start of valid data depends on which timing becomes effective last t
Timing Waveform of Read Cycle No. 2, Either Side
ADDRESS
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = V
4. Start of valid data depends on which timing becomes effective last t
DATA
BUSY
DATA
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
BUSY has no relationship to valid output data.
BDD
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
I
OUT
I
OE
OUT
CE
OUT
CC
SS
IH
IH
, CE = V
and OE = V
PREVIOUS DATA VALID
IL
, and is OE = V
IL
, and the address is valid prior to or coincidental with CE transition LOW.
IL
t
. Address is valid prior to the coincidental with CE transition LOW.
OH
t
t
PU
AA
50%
t
LZ
(1)
t
ACE
t
RC
AOE
AOE
t
t
LZ
BDDH
, t
t
, t
(1)
AOE
ACE
ACE
(2,3)
,
, t
(4)
6.42
t
AA
AA
8
, and
, and t
t
DATA VALID
BDD
BDD
.
.
Industrial and Commercial Temperature Ranges
VALID DATA
(1)
(3)
t
OH
t
PD
t
HZ
(4)
(2)
t
HZ
(2)
50%
2691 drw 06
2691 drw 07

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