IDT71321SA55J IDT, Integrated Device Technology Inc, IDT71321SA55J Datasheet - Page 16

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IDT71321SA55J

Manufacturer Part Number
IDT71321SA55J
Description
IC SRAM 16KBIT 55NS 52PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71321SA55J

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
16K (2K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
71321SA55J

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Functional Description
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT71321/IDT71421 has an automatic
power down feature controlled by CE. The CE controls on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = V
memory array is permitted.
Interrupts
or message center) is assigned to each port. The left port interrupt flag
(INT
(HEX), where a write is defined as the CE
II. The left port clears the interrupt by accessing address location 7FE when
CE
flag (INT
(HEX) and to clear the interrupt flag (INT
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
Busy Logic
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write from proceeding.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. In slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
outputs and require open drain resistors to operate. If these SRAMs are
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
L
The IDT71321/IDT71421 provides two ports with separate control,
If the user chooses the interrupt function, a memory location (mail box
Busy Logic provides a hardware indication that both ports of the RAM
The use of BUSY Logic is not required or desirable for all applications.
The BUSY outputs on the IDT71321 (Master) are open drain type
L
= OE
) is asserted when the right port writes to memory location 7FE
R
L =
) is asserted when the left port writes to memory location 7FF
V
IL,
R/W
is a "don't care". Likewise, the right port interrupt
IH
). When a port is enabled, access to the entire
R
), the right port must access the
R
= R/W
R
= V
IL,
per Truth Table
6.42
16
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
master part is used to decide which side of the SRAM array will receive
a BUSY indication, and to output that indication. Any number of slaves to
be addressed in the same address range as the master, use the BUSY
signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs
the BUSY pin is an output if the part is Master (IDT71321), and the BUSY
pin is an input if the part is a Slave (IDT71421) as shown in Figure 3.
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
270Ω
BUSY
When expanding an SRAM array in width while using BUSY logic, one
Figure 3. Busy and chip enable routing for both width and depth
If two or more master parts were used when expanding in width, a split
The BUSY arbitration, on a Master, is based on the chip enable and
5V
expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.
L
MASTER
Dual Port
SRAM
BUSY
MASTER
Dual Port
SRAM
BUSY
Industrial and Commercial Temperature Ranges
L
L
BUSY
BUSY
CE
CE
R
R
SLAVE
Dual Port
SRAM
BUSY
SLAVE
Dual Port
SRAM
BUSY
L
L
BUSY
BUSY
CE
CE
R
R
2691 drw 16
BUSY
5V
R
270Ω
,

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