IDT71321SA55J IDT, Integrated Device Technology Inc, IDT71321SA55J Datasheet - Page 15

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IDT71321SA55J

Manufacturer Part Number
IDT71321SA55J
Description
IC SRAM 16KBIT 55NS 52PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT71321SA55J

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
16K (2K x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
52-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
71321SA55J

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Truth Tables
Truth Table I. Non-Contention Read/Write Control
Truth Table II. Interrupt Flag
NOTES:
1. Assumes BUSY
2. If BUSY
3. If BUSY
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Truth Table III — Address BUSY Arbitration
NOTES:
1. Pins BUSY
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
3. Writes to the left port are internally ignored when BUSY
NOTES:
1. A
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see t
4. 'H' = V
CE
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
X
H
X
L
pull outputs. On slaves the BUSY
and enable inputs of this port. If t
when BUSY
R/W
R/W
L
X
X
H
H
0L
X
X
X
L
L
L
– A
CE
IH
10L
L
R
X
X
H
L
, 'L' = V
R
= V
= V
Inputs
L
≠ A
R
and BUSY
CE
IL
Left or Right Port
IL
CE
outputs are driving LOW regardless of actual logic level on the pin.
H
H
X
X
L
L
L
L
L
, then No Change.
0R
, then No Change.
L
NO MATCH
L
IL
A
= BUSY
A
MATCH
MATCH
MATCH
– A
, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
0R
0L
-A
-A
10R
R
10L
10R
Left Port
.
R
are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSY
OE
OE
X
X
X
L
H
X
X
X
L
= V
L
IH
(1)
BUSY
APS
X
(2)
H
H
H
is not met, either BUSY
input internally inhibits writes.
A
DATA
L
DATA
10L
7FE
Outputs
7FF
(1)
D
X
X
WDD
-A
Z
Z
Z
0-7
OUT
0L
IN
BUSY
and t
(2)
H
H
H
DDD
Port Disabled and in Power-Down Mode, ISB
Data on Port Written Into Memory
Data in Memory Output on Por
High Impedance Outputs
CE
R
L
(1)
INT
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
H
X
X
L
R
timing.
(3)
(2)
L
= CE
Write Inhibit
L
or BUSY
Function
L
(1,4)
Normal
Normal
Normal
= V
R/W
X
X
X
L
2691 tbl 14
IH
, Power-Down Mode, ISB
R
R
(3)
= LOW will result. BUSY
6.42
15
CE
X
X
L
L
R
t
(3)
(2)
Right Port
OE
X
X
X
L
R
1
L
or ISB
Industrial and Commercial Temperature Ranges
2
and BUSY
Function
or ISB
A
3
10R
7FF
7FE
X
X
X
-A
4
(4)
R
0R
outputs on the IDT71321 are open drain, not push-
outputs can not be LOW simultaneously.
INT
H
X
X
L
(2)
(3)
R
Set Right INT
Reset Right INT
Set Left INT
Reset Left INT
Function
L
R
Flag
L
Flag
R
Flag
Flag
2691 tbl 12
2691 tbl 13

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