MT46V64M16P-75:A TR Micron Technology Inc, MT46V64M16P-75:A TR Datasheet - Page 78
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MT46V64M16P-75:A TR
Manufacturer Part Number
MT46V64M16P-75:A TR
Description
IC DDR SDRAM 1GBIT 7.5NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16P-75:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
250mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 50:
AUTO REFRESH
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Command
BA0, BA1
Address
DQS
CK#
CKE
A10
DQ
DM
CK
4
t IS
t IS
NOP
T0
Bank WRITE – with Auto Precharge
t IH
1
t IH
Notes:
t IS
t IS
Bank x
ACT
Row
Row
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at these
2. BL = 4.
3. Enable auto precharge.
4. DI n = data-out from column n; subsequent elements are provided in the programmed
5. See Figure 48 on page 76 for detailed DQ timing.
During auto refresh, the addressing is generated by the internal refresh controller. This
makes the address bits a “Don’t Care” during an AUTO REFRESH command. The DDR
SDRAM requires AUTO REFRESH cycles at an average interval of
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 9 ×
specifications exceed the JEDEC requirement by one clock. This maximum absolute
interval is to allow future support for DLL updates, internal to the DDR SDRAM, to be
restricted to AUTO REFRESH cycles, without allowing excessive drift in
updates.
t IH
t IH
times.
order.
t CK
t RCD
t RAS
NOP
T2
1
t CH
t
REFI(=
t CL
t IS
Bank x
3
WRITE
Col n
T3
t IH
t DQSS (NOM)
2
t
REFC). JEDEC specifications only support 8 ×
t WPRES t WPRE
t DS
78
NOP
T4
DI
b
1
t DH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4n
t DQSL
NOP
T5
t DQSH
1
1Gb: x4, x8, x16 DDR SDRAM
T5n
t WPST
NOP
T6
1
Transitioning Data
©2003 Micron Technology, Inc. All rights reserved.
t
REFI (MAX).
t WR
NOP
T7
1
t
t
REFI; Micron
AC between
Operations
Don’t Care
NOP
T8
1
t RP