MT46V64M16P-75:A TR Micron Technology Inc, MT46V64M16P-75:A TR Datasheet - Page 69
![IC DDR SDRAM 1GBIT 7.5NS 66TSOP](/photos/7/22/72288/mfg557-66-tsop_sml.jpg)
MT46V64M16P-75:A TR
Manufacturer Part Number
MT46V64M16P-75:A TR
Description
IC DDR SDRAM 1GBIT 7.5NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16P-75:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
250mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 41:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
WRITE-to-READ – Interrupting
DQ
DQ
DQ
CK
Notes:
Bank a,
WRITE
Col b
T0
t
t
t
1. DI b = data-in for column b; DO n = data-out for column n.
2. An interrupted burst of 4 is shown; two data elements are written.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. DQS is required at T2 and T2n (nominal case) to register DM.
7. If the burst of 8 is used, DM and DQS are required at T3 and T3n because the READ com-
DQSS
DQSS
DQSS
t
mand will not mask these two data elements.
WTR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
t
WTR
69
T2n
Bank a,
READ
Col n
T3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3n
CL = 2
CL = 2
CL = 2
T4
NOP
1Gb: x4, x8, x16 DDR SDRAM
Transitioning Data
©2003 Micron Technology, Inc. All rights reserved.
T5
NOP
DO
DO
DO
n
n
n
T5n
Operations
T6
NOP
Don’t Care
T6n