MT46V64M16P-75:A TR Micron Technology Inc, MT46V64M16P-75:A TR Datasheet - Page 62
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MT46V64M16P-75:A TR
Manufacturer Part Number
MT46V64M16P-75:A TR
Description
IC DDR SDRAM 1GBIT 7.5NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16P-75:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
250mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 34:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
x16 Data Output Timing –
DQ8–DQ15 and UDQS collectively
DQ0–DQ7 and LDQS collectively
DQ (first data no longer valid)
DQ (first data no longer valid)
DQ (first data no longer valid)
DQ (first data no longer valid)
Notes:
DQ (last data valid)
DQ (last data valid)
DQ (last data valid)
DQ (last data valid)
1.
2.
3. DQ transitioning after DQS transition define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5.
6. The data valid window is derived for each DQS transition and is
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
t
t
transition, and ends with the last valid DQ transition.
byte, and UDQS defines the upper byte.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
UDQS
LDQS 3
CK#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
4
4
4
4
4
4
4
4
4
4
6
3
7
7
7
7
7
7
7
7
7
7
6
T1
t HP 1
t
DQSQ,
t
CL or
t
HP:
t HP 1
t
t
t
QH =
QH, and Data Valid Window
CH clock transition collectively when a bank is active.
t DQSQ 2
t QH 5
62
t DQSQ 2
T2
t
t QH 5
HP -
Data valid
window
T2
T2
T2
Data valid
t HP 1
window
t
QHS.
T2
T2
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2n
t DQSQ 2
t QH 5
t DQSQ 2
t QH 5
Data valid
window
t HP 1
T2n
T2n
T2n
Data valid
window
t
DQSQ window. LDQS defines the lower
T2n
T2n
T2n
1Gb: x4, x8, x16 DDR SDRAM
T3
t DQSQ 2
t QH 5
t DQSQ 2
t QH 5
t HP 1
Data valid
window
Data valid
T3
T3
T3
window
T3
T3n
T3
T3
©2003 Micron Technology, Inc. All rights reserved.
t
QH -
t DQSQ 2
t DQSQ 2
t HP 1
t QH 5
t QH 5
t
DQSQ.
Data valid
window
Data valid
T4
T3n
window
T3n
T3n
T3n
T3n
T3n
Operations