MT46V64M16P-75:A TR Micron Technology Inc, MT46V64M16P-75:A TR Datasheet - Page 59
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MT46V64M16P-75:A TR
Manufacturer Part Number
MT46V64M16P-75:A TR
Description
IC DDR SDRAM 1GBIT 7.5NS 66TSOP
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46V256M4P-6TA_TR.pdf
(82 pages)
Specifications of MT46V64M16P-75:A TR
Format - Memory
RAM
Memory Type
DDR SDRAM
Memory Size
1G (64M x 16)
Speed
7.5ns
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
66-TSOP
Organization
64Mx16
Density
1Gb
Address Bus
16b
Access Time (max)
750ps
Maximum Clock Rate
266MHz
Operating Supply Voltage (typ)
2.5V
Package Type
TSOP
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Supply Current
250mA
Pin Count
66
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 31:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
READ-to-PRECHARGE
Notes:
Command
Command
Command
Address
Address
Address
1. Provided
2. DO n = data-out from column n.
3. BL = 4 or an interrupted burst of 8.
4. Three subsequent elements of data-out appear in the programmed order following DO n.
5. Shown with nominal
6. READ-to-PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also
7. An ACTIVE command to the same bank is only allowed if
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
CK
CK
CK
precharge to be performed at x number of clock cycles after the READ command, where
x = BL/2.
assumed that
Bank a,
Bank a,
Bank a,
READ
READ
READ
Col n
Col n
Col n
T0
T0
T0
t
RAS (MIN) is met, a READ command with auto precharge enabled would cause a
t
RAS (MIN) is met.
t
CL = 2
AC,
NOP
NOP
NOP
T1
T1
T1
CL = 2.5
t
DQSCK, and
CL = 3
59
(a or all)
(a or all)
(a or all)
Bank a,
Bank a,
Bank a,
T2
PRE
PRE
PRE
T2
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
DQSQ.
DO
n
T2n
T2n
DO
n
1Gb: x4, x8, x16 DDR SDRAM
T3
NOP
T3
NOP
T3
NOP
DO
n
t RP
t RP
t RP
t
T3n
T3n
T3n
RC (MIN) is met.
Transitioning Data
©2003 Micron Technology, Inc. All rights reserved.
T4
NOP
T4
T4
NOP
NOP
T4n
Operations
Bank a,
Bank a,
Bank a,
T5
T5
T5
Row
ACT
ACT
Row
ACT
Row
Don’t Care