MT46H16M16LFBF-6 IT:A TR Micron Technology Inc, MT46H16M16LFBF-6 IT:A TR Datasheet - Page 52
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MT46H16M16LFBF-6 IT:A TR
Manufacturer Part Number
MT46H16M16LFBF-6 IT:A TR
Description
IC DDR SDRAM 256MBIT 60VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT46H16M16LFBF-6A_TR.pdf
(79 pages)
Specifications of MT46H16M16LFBF-6 IT:A TR
Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (16Mx16)
Speed
166MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
60-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1278-2
Table 10:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Current State
Any
Idle
Row active
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
Truth Table – Current State Bank n – Command to Bank n
Notes 1–6 apply to all states listed in this table; notes appear below and on next page
Notes:
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table is bank-specific, except where noted (for example, the current state is for a spe-
3. Current state definitions:
4.
RAS#
H
X
H
H
H
H
H
H
H
the previous state was SELF REFRESH), after
power-down), or 200µs if the previous state was DPD.
cific bank and the commands shown are those allowed to be issued to that bank when in
that state). Exceptions are discussed in the notes below.
bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank
should be issued on any clock edge occurring during these states. Allowable commands to
any other bank are determined by that bank’s current state.
L
L
L
L
L
L
Idle:
Row active:
Read:
Write:
Precharging:
Row activating:
Read with auto
precharge
enabled:
Write with auto
precharge
enabled:
CAS#
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
The following states must not be interrupted by a command issued to the same
WE#
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
The bank has been precharged, and
A row in the bank has been activated, and
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Starts with registration of a PRECHARGE command and ends when
is met. When
Starts with registration of an ACTIVE command and ends when
met. When
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
Command (Action)
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
n - 1
52
t
was HIGH and CKE
RCD is met, the bank will be in the row active state.
t
RP is met, the bank will be in the idle state.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
t
t
t
RP has been met. When
XP has been met (if the previous state was
RP has been met. When
n
is HIGH and after
t
RP has been met.
t
RCD has been met. No data
©2005 Micron Technology, Inc. All rights reserved.
t
RP is met, the bank
t
t
RP is met, the bank
XSR has been met (if
Operations
Notes
10, 12
10, 11
8, 11
t
RCD is
10
10
10
10
7
7
8
8
9
t
RP