MT46H8M32LFB5-5 IT:H TR Micron Technology Inc, MT46H8M32LFB5-5 IT:H TR Datasheet - Page 77
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MT46H8M32LFB5-5 IT:H TR
Manufacturer Part Number
MT46H8M32LFB5-5 IT:H TR
Description
IC DDR SDRAM 256MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT46H16M16LFBF-5H.pdf
(96 pages)
Specifications of MT46H8M32LFB5-5 IT:H TR
Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (8Mx32)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 40: WRITE-to-READ – Odd Number of Data, Interrupting
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
4
5
4
5
4
5
1
WRITE
Bank a,
Col b
T0
Notes:
t
t
t
DQSS
DQSS
DQSS
2
1. An interrupted burst of 4 is shown; 1 data element is written, 3 are masked.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. D
D
IN
t
NOP
WTR is referenced from the first positive CK edge after the last data-in pair.
D
T1
IN
IN
b = data-in for column b; D
D
IN
T1n
NOP
T2
t
WTR
T2n
3
77
Bank a,
READ
Col b
T3
OUT
256Mb: x16, x32 Mobile LPDDR SDRAM
n = data-out for column n.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T4
NOP
CL = 3
CL = 3
CL = 3
Don’t Care
T5
NOP
©2008 Micron Technology, Inc. All rights reserved.
WRITE Operation
T5n
Transitioning Data
D
D
D
OUT
OUT
OUT
T6
NOP
D
D
D
OUT
OUT
OUT
T6n
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