NetduinoPlus2 Netduino, NetduinoPlus2 Datasheet - Page 34

• Manufacturer Part Number: NetduinoPlus2
• Description: Development Boards & Kits - ARM NETDUINO PLUS 2
• Manufacturer: Netduino

Specifications of NetduinoPlus2

• Rohs: yes
• Product: Development Boards
• Tool Is For Evaluation Of: STM32F405RG
• Core: ARM Cortex M4
• Interface Type: I2C, SPI, UART, USB
• Operating Supply Voltage: 7.5 v to 9 V
• Data Bus Width: 32 bit
• Description/function: Arduino form factor
• Dimensions: 2.8 in x 2.1 in
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C

Description
2.2.28
2.2.29
2.2.30
34/180
The STM32F407xx includes the following features:
●
●
●
●
●
●
●
●
●
●
●
Controller area network (bxCAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1
Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). 256 bytes of SRAM are allocated for each CAN.
Universal serial bus on-the-go full-speed (OTG_FS)
The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG
peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the
USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable
endpoint setting and supports suspend/resume. The USB OTG full-speed controller
requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE
oscillator. The major features are:
●
●
●
●
●
●
Universal serial bus on-the-go high-speed (OTG_HS)
The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to
480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and
high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and
features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using
the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required.
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors (see the STM32F46x reference manual for details)
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and group
addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive
FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
Doc ID 022152 Rev 3
STM32F405xx, STM32F407xx