AT45DB021D-SH-T Atmel, AT45DB021D-SH-T Datasheet - Page 32

• Manufacturer Part Number: AT45DB021D-SH-T
• Description: IC FLASH 2MBIT 66MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT45DB021D-SH-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 2M (1024 pages x 264 bytes)
• Speed: 66MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Cell Type: NOR
• Density: 2Mb
• Access Time (max): 6ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256K
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16. Power-on/Reset State
16.1
17. System Considerations
32
Initial Power-up/Reset Timing Restrictions
AT45DB021D
When power is first applied to the device, or when recovering from a reset condition, the device
will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a
high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode
3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive
clock state.
At power up, the device must not be selected until the supply voltage reaches the V
further delay of t
reset mode until the V
operations are disabled and the device does not respond to any commands. After power up is
applied and the V
before the device can be selected in order to perform a read operation.
Similarly, the t
value (V
power-up, the device will default in Standby mode.
The serial interface is controlled by the clock SCK, serial input SI and chip select CS pins. These
signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on
these pins can be misinterpreted as multiple edges and cause improper operation of the device.
The PC board traces must be kept to a minimum distance or appropriately terminated to ensure
proper operation. If necessary, decoupling capacitors can be added on these pins to provide fil-
tering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak current for DataFlash occur during the programming and erase operation.
The regulator needs to supply this peak current requirement. An under specified regulator can
cause current starvation. Besides increasing system noise, current starvation during program-
ming or erase can lead to improper operation and possible data corruption.
In an effort to continue our goal of maintaining world-class quality leadership, Atmel has been
performing extensive testing on the AT45DB021D that would not normally be done with a Serial
Flash device. The testing that has been performed on the AT45DB021D involved extensive,
non-stop reading of the memory array on pre-conditioned devices. The pre-conditioning of the
devices, which entailed erasing and programming the entire memory array 10,000 times, was
done to simulate a customer environment and to exercise the memory cells to a certain degree.
The non-stop reading of the devices was done in three levels of granularity, with the first level
involving a continuous, looped read of 256 bytes (a single page) of memory, the second level
involving a continuous, looped-read of a 4-Kbyte (16 pages) portion of memory, and the third
level entailing non-stop reading of the entire memory array. Read operations were performed at
Symbol
t
t
V
VCSL
PUW
POR
POR
) before the device can perform a write (Program or Erase) operation. After initial
Parameter
V
Power-Up Device Delay before Write Allowed
Power-On Reset Voltage
CC
PUW
VCSL
(min.) to Chip Select low
CC
delay is required after the V
. During power-up, the internal Power-on Reset circuitry keeps the device in
is at the minimum operating voltage V
CC
rises above the Power-on Reset threshold value (V
CC
rises above the Power-on Reset threshold
Min
1.5
CC
1
(min.), the t
Typ
VCSL
POR
delay is required
Max
). At this time, all
2.5
3638I–DFLASH–04/09
20
CC
(min.) and
Units
ms
ms
V