C8051F313R Silicon Labs, C8051F313R Datasheet - Page 180

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C8051F313R

Manufacturer Part Number
C8051F313R
Description
8-bit Microcontrollers - MCU 8KB 10ADC
Manufacturer
Silicon Labs
Datasheet

Specifications of C8051F313R

Product Category
8-bit Microcontrollers - MCU
Core
8051
Data Bus Width
8 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
8 KB
Data Ram Size
1.25 KB
On-chip Adc
Yes
Operating Supply Voltage
2.7 V to 3.6 V
Package / Case
QFN-28
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
17
Data Rom Size
128 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
25
Number Of Timers
5
On-chip Dac
No
Processor Series
C8051
Program Memory Type
Flash
Factory Pack Quantity
1500
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
C8051F310/1/2/3/4/5/6/7
16.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following register definitions.
180
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
*Note:
SPIBSY
Bit7
R
SPIBSY: SPI Busy (read only).
This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode).
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data centered on first edge of SCK period.*
1: Data centered on second edge of SCK period.*
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
SLVSEL: Slave Selected Flag (read only).
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It
is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the
instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.
NSSIN: NSS Instantaneous Pin Input (read only).
This bit mimics the instantaneous value that is present on the NSS port pin at the time that
the register is read. This input is not de-glitched.
SRMT: Shift Register Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift register,
and there is no new information available to read from the transmit buffer or write to the
receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from
the transmit buffer or by a transition on SCK.
NOTE: SRMT = 1 when in Master Mode.
RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when the receive buffer has been read and contains no new
information. If there is new information available in the receive buffer that has not been read,
this bit will return to logic 0.
NOTE: RXBMT = 1 when in Master Mode.
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave
device. See Table 16.1 for timing parameters.
In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
MSTEN
R/W
Bit6
SFR Definition 16.1. SPI0CFG: SPI0 Configuration
CKPHA
R/W
Bit5
CKPOL
R/W
Bit4
SLVSEL
Rev. 1.7
Bit3
R
NSSIN
Bit2
R
SRMT
Bit1
R
SFR Address: 0xA1
RXBMT
Bit0
R
Reset Value
00000111

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