MT47H32M8BP-37E:B TR Micron Technology Inc, MT47H32M8BP-37E:B TR Datasheet - Page 104
![IC DDR2 SDRAM 256MBIT 60FBGA](/photos/7/23/72317/mfg557-60-fbga_sml.jpg)
MT47H32M8BP-37E:B TR
Manufacturer Part Number
MT47H32M8BP-37E:B TR
Description
IC DDR2 SDRAM 256MBIT 60FBGA
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H16M16BG-3B_TR.pdf
(128 pages)
Specifications of MT47H32M8BP-37E:B TR
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
256M (32M x 8)
Speed
3.75ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Organization
32Mx8
Density
256Mb
Address Bus
15b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
160mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1049-2
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Figure 61: WRITE-to-PRECHARGE
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
Command
Address
t DQSS (NOM)
t DQSS (MIN)
t DQSS (MAX)
DQS#
DQS#
DQS#
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Bank a,
WRITE
Col b
T0
Notes:
WL + t DQSS
WL - t DQSS
WL + t DQSS
NOP
1. Subsequent rising DQS signals must align to the clock within
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
4. BL = 4, CL = 3, AL = 0; thus, WL = 2.
5.
6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
7. A10 is LOW with the WRITE command (auto precharge is disabled).
T1
DI b.
t
and WRITE commands may be to different banks, in which case
the PRECHARGE command could be applied earlier.
WR is referenced from the first positive CK edge after the last data-in pair.
DI
b
NOP
T2
DI
b
DI
b
T2n
1
NOP
1
T3
104
1
T3n
T4
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 DDR2 SDRAM
T5
NOP
Transitioning Data
t WR
©2003 Micron Technology, Inc. All rights reserved.
t
T6
DQSS.
NOP
t
WR is not required and
(a or all)
T7
Bank,
PRE
Don’t Care
t RP
WRITE
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