LH28F160S3T-L10A Sharp Microelectronics, LH28F160S3T-L10A Datasheet - Page 9

• Manufacturer Part Number: LH28F160S3T-L10A
• Description: IC FLASH 16MBIT 100NS 56TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F160S3T-L10A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 425-1838; LHF16KA6

sharp
2.1 Data Protection
Depending on the application, the system designer
may choose to make the V
switchable (available only when block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to V
The device accommodates either design practice and
encourages optimization of the processor-memory
interface.
When V
altered. The CUI, with multi-step block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration
protection from unwanted operations even when high
voltage is applied to V
disabled when V
V
locking capability provides additional protection from
inadvertent code or data alteration by gating block
erase, full chip erase and (multi) word/byte write
operations.
3 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, query structure, or status register independent
of the V
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, Query
or Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-down
mode, the device automatically resets to read array
mode. Five control pins dictate the data flow in and
out of the component: CE# (CE
RP# and WP#. CE
active to obtain data at the outputs. CE
the device selection control, and when active enables
the selected memory device. OE# is the data output
(DQ
selected memory data onto the I/O bus. WE# and
RP# must be at V
cycle.
LKO
0
-DQ
or when RP# is at V
PP
15
PP
voltage. RP# must be at V
) control and when active drives the
≤V
PPLK
command
CC
IH
, memory contents cannot be
0
#, CE
is below the write lockout voltage
. Figure 17, 18 illustrates a read
PP
1
# and OE# must be driven
. All write functions are
sequences,
IL
0
. The device’s block
#, CE
PP
IH
1
power supply
.
#), OE#, WE#,
0
#, CE
provides
PPH1/2/3
1
# is
LHF16KA6
.
3.2 Output Disable
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.3 Standby
Either CE
the device in standby mode which substantially
reduces device power consumption. DQ
outputs are placed in a high-impedance state
independent of OE#. If deselected during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at V
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time t
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-low
will abort the operation. STS remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time t
goes to logic-high (V
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, full
chip erase, (multi) word/byte write and block lock-bit
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP’s
flash memories allow proper CPU initialization
following a system reset through the use of the RP#
input. In this application, RP# is controlled by the
same RESET# signal that resets the system CPU.
IL
0
# or CE
initiates the deep power-down mode.
1
# at a logic-high level (V
IH
) before another command can
PHWL
PHQV
is required after RP#
is required after
IH
), the device
0
-DQ
IH
Rev. 2.0
) places
0
15
-DQ
are
15
7