LH28F160S3T-L10A Sharp Microelectronics, LH28F160S3T-L10A Datasheet - Page 8

• Manufacturer Part Number: LH28F160S3T-L10A
• Description: IC FLASH 16MBIT 100NS 56TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F160S3T-L10A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 425-1838; LHF16KA6

sharp
2 PRINCIPLES OF OPERATION
The LH28F160S3T-L10A Flash memory includes an
on-chip WSM to manage block erase, full chip erase,
(multi)
configuration functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, and minimal processor
overhead with RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register, query structure and identifier codes
can be accessed through the CUI independent of the
V
block erase, full chip erase, (multi) word/byte write
and
associated with altering memory contentsblock
erase, full chip erase, (multi) word/byte write and
block
identifier codesare accessed via the CUI and
verified through the status register.
Commands
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
full chip erase, (multi) word/byte write and block lock-
bit
regulated by the WSM, including pulse repetition,
internal
Addresses and data are internally latch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, outputs
query structure or outputs status register data.
Interface software that initiates and polls progress of
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
read or write data from any other block. Write
suspend allows system software to suspend a (multi)
word/byte write to read data from any other flash
memory array location.
PP
voltage. High voltage on V
configuration.
block
lock-bit configuration, status, query and
word/byte
verification,
lock-bit
are
The
write
configuration.
written
and
internal
and
margining
PP
enables successful
using
algorithms
block
All
of
functions
standard
lock-bit
data.
are
LHF16KA6
1DFFFF
1CFFFF
0DFFFF
0CFFFF
1FFFFF
1EFFFF
1BFFFF
1AFFFF
0FFFFF
0EFFFF
0BFFFF
0AFFFF
19FFFF
18FFFF
17FFFF
16FFFF
15FFFF
14FFFF
13FFFF
12FFFF
11FFFF
10FFFF
09FFFF
08FFFF
07FFFF
06FFFF
05FFFF
04FFFF
03FFFF
02FFFF
01FFFF
00FFFF
1E0000
1D0000
1C0000
1B0000
1A0000
0E0000
0D0000
0C0000
0B0000
0A0000
1F0000
190000
180000
170000
160000
150000
140000
130000
120000
110000
100000
0F0000
090000
080000
070000
060000
050000
040000
030000
020000
010000
000000
Figure 3. Memory Map
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
64K-byte Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rev. 2.0
6