LH28F160S3T-L10A Sharp Microelectronics, LH28F160S3T-L10A Datasheet - Page 5

• Manufacturer Part Number: LH28F160S3T-L10A
• Description: IC FLASH 16MBIT 100NS 56TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F160S3T-L10A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 425-1838; LHF16KA6

sharp
1 INTRODUCTION
This
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
1.1 Product Overview
The LH28F160S3T-L10A is a high-performance 16M-
bit
2MBx8/1MBx16. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
Smart 3 technology provides a choice of V
V
system performance and power expectations. 2.7V
V
5V V
need for a separate 12V converter, while V
maximizes erase and write performance. In addition
to flexible erase and program voltages, the dedicated
V
V
Internal
automatically configures the device for optimized
read and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.41s (3.3V V
V
independently erased 100,000 times (3.2 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
A word/byte write is performed in byte increments
typically within 12.95µs (3.3V V
word/byte write has high speed write performance of
2.7µs/byte (3.3V V
PP
CC
PP
PP
PP
Table 1. V
≤V
) independent of other blocks. Each block can be
consumes approximately one-fifth the power of
Smart
combinations, as shown in Table 1, to meet
CC
pin gives complete data protection when
PPLK
V
datasheet
. V
CC
Offered by Smart 3 Technology
V
2.7V
3.3V
.
PP
Voltage
CC
CC
3
at 2.7V, 3.3V and 5V eliminates the
and V
and
Flash
CC
contains
, 5V V
PP
V
Voltage Combinations
PP
memory
PP
CC
LH28F160S3T-L10A
2.7V, 3.3V, 5V
detection
). (Multi) Word/byte
V
, 5V V
PP
3.3V, 5V
organized
Voltage
PP
). A multi
Circuitry
CC
CC
PP
, 5V
=5V
and
LHF16KA6
as
write suspend mode enables the system to read data
or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits
and WP#, Thirty-two block lock-bits, to lock and
unlock blocks. Block lock-bits gate block erase, full
chip erase and (multi) word/byte write operations.
Block lock-bit configuration operations (Set Block
Lock-Bit and Clear Block Lock-Bits commands) set
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults to
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
The access time is 100ns (t
commercial temperature range (0°C to +70°C) and
V
voltage, the access time is 120ns (2.7V-3.6V).
The
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
mode, the typical I
When either CE
the I
RP# pin is at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(t
outputs are valid. Likewise, the device has a wake
time (t
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
PHQV
CC
CC
supply voltage range of 3.0V-3.6V. At lower V
Automatic
) is required from RP# switching high until
PHEL
CMOS standby mode is enabled. When the
software
) from RP#-high until writes to the CUI are
0
# or CE
CCR
Power
polling)
current is 3 mA at 3.3V V
1
#, and RP# pins are at V
Savings
and
AVQV
status
(APS)
) over the
Rev. 2.0
masking
feature
CC
CC
.
CC
3
,