LH28F160S3T-L10A Sharp Microelectronics, LH28F160S3T-L10A Datasheet - Page 22

• Manufacturer Part Number: LH28F160S3T-L10A
• Description: IC FLASH 16MBIT 100NS 56TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F160S3T-L10A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 16M (2M x 8 or 1M x 16)
• Speed: 100ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 425-1838; LHF16KA6

sharp
SR.7 = WRITE STATE MACHINE STATUS
SR.6 = BLOCK ERASE SUSPEND STATUS
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
SR.3 = V
SR.2 = WRITE SUSPEND STATUS
SR.1 = DEVICE PROTECT STATUS
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
XSR.7 = STATE MACHINE STATUS
XSR.6-0=RESERVED FOR FUTURE ENHANCEMENTS
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Erase or Clear Blocl Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
1 = V
0 = V
1 = Write Suspended
0 = Write in Progress/Completed
1 = Block Lock-Bit and/or WP# Lock Detected,
0 = Unlock
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available
SMS
7
7
STATUS
Operation Abort
PP
PP
PP
STATUS
Low Detect, Operation Abort
OK
BESS
R
6
6
ECBLBS
Table 14.1. Extended Status Register Definition
R
5
5
Table 14. Status Register Definition
WSBLBS
R
4
4
LHF16KA6
NOTES:
Check STS or SR.7 to determine block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration completion.
SR.6-0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full
chip erase, (multi) word/byte write, block lock-bit
configuration or STS configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of V
level. The WSM interrogates and indicates the V
only after block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration command
sequences. SR.3 is not guaranteed to reports accurate
feedback only when V
SR.1 does not provide a continuous indication of block
lock-bit values. The WSM interrogates block lock-bit,
and WP# only after block erase, full chip erase, (multi)
word/byte write or block lock-bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set and/or
WP# is not V
codes after writing the Read Identifier Codes command
indicates block lock-bit status.
SR.0 is reserved for future use and should be masked
out when polling the status register.
NOTES:
After issue a Multi Word/Byte Write command: XSR.7
indicates that a next Multi Word/Byte Write command is
available.
XSR.6-0 is reserved for future use and should be
masked out when polling the extended status register.
VPPS
R
3
3
IH
. Reading the block lock configuration
WSS
R
2
2
PP
≠V
PPH1/2/3
DPS
R
1
.
1
PP
Rev. 2.0
R
R
0
0
PP
level
20