ST72C334J2B6 STMicroelectronics, ST72C334J2B6 Datasheet - Page 96
ST72C334J2B6
Manufacturer Part Number
ST72C334J2B6
Description
8-bit Microcontrollers - MCU Flash 8K SPI/SCI
Manufacturer
STMicroelectronics
Datasheet
1.ST72C334J2B6.pdf
(153 pages)
Specifications of ST72C334J2B6
Product Category
8-bit Microcontrollers - MCU
Core
ST7
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Program Memory Size
8 KB
Data Ram Size
384 B
On-chip Adc
Yes
Operating Supply Voltage
3.2 V to 5.5 V
Package / Case
SDIP-42
Mounting Style
Through Hole
A/d Bit Size
8 bit
A/d Channels Available
8
Data Rom Size
256 B
Interface Type
SCI, SPI
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
32
Number Of Timers
4 bit
Program Memory Type
Flash
Factory Pack Quantity
13
Supply Voltage - Max
5 V
Supply Voltage - Min
3.2 V
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Quantity
Price
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Part Number:
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Manufacturer:
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ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (ERPR)
Read/Write
Reset Value: 0000 0000 (00 h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Bit 7:1 = ERPR[7:0] 8-bit Extended Receive Pres-
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 3.) is divided by the
binary factor set in the ERPR register (in the range
1 to 255).
The extended baud rate generator is not used af-
ter a reset.
Table 18. SCI Register Map and Reset Values
96/153
ERPR
Address
(Hex.)
7
7
0050h
0051h
0052h
0053h
0054h
0055h
0057h
ERPR
6
SCISR
Reset Value
SCIDR
Reset Value
SCIBRR
Reset Value
SCICR1
Reset Value
SCICR2
Reset Value
SCIPBRR
Reset Value
SCIPBRT
Reset Value
Register
ERPR
Label
5
ERPR
4
TDRE
ERPR
MSB
SOG
MSB
MSB
TIE
R8
7
3
1
x
0
x
0
0
0
ERPR
2
TCIE
TC
T8
6
0
1
x
0
x
0
0
ERPR
1
ERPR
RDRF
VPOL
0
0
RIE
5
0
x
x
0
0
0
0
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)
Read/Write
Reset Value:0000 0000 (00h)
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
Bit 7:1 = ETPR[7:0] 8-bit Extended Transmit Pres-
caler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 3.) is divided by the
binary factor set in the ETPR register (in the range
1 to 255).
The extended baud rate generator is not used af-
ter a reset.
2FHDET
ETPR
IDLE
ILIE
7
7
M
4
0
x
x
x
0
0
0
ETPR
6
HVSEL
WAKE
OR
TE
ETPR
3
0
0
0
0
x
x
x
5
ETPR
VCORDIS
4
RE
NF
2
0
0
0
0
0
x
x
ETPR
3
CLPINV
RWU
ETPR
FE
1
0
x
x
0
0
0
0
2
ETPR
1
BLKINV
SBK
LSB
LSB
LSB
0
0
0
0
0
0
x
x
ETPR
0
0
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