CY7C1520JV18-300BZC Cypress Semiconductor Corp, CY7C1520JV18-300BZC Datasheet - Page 26
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CY7C1520JV18-300BZC
Manufacturer Part Number
CY7C1520JV18-300BZC
Description
IC SRAM 72MBIT 300MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1520JV18-300BZXC.pdf
(26 pages)
Specifications of CY7C1520JV18-300BZC
Format - Memory
RAM
Memory Type
SRAM - Synchronous, DDR II
Memory Size
72M (2M x 36)
Speed
300MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1520JV18-300BZC
Manufacturer:
SMD
Quantity:
1 988
Company:
Part Number:
CY7C1520JV18-300BZC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY7C1520JV18-300BZC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document History Page
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12559 Rev. *C
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document Title: CY7C1516JV18/CY7C1527JV18/CY7C1518JV18/CY7C1520JV18, 72-Mbit DDR-II SRAM 2-Word
Burst Architecture
Document Number: 001-12559
REV.
*A
*B
*C
**
ECN NO.
1273883 See ECN
1462589 See ECN
2189567 See ECN
808457
See ECN
ISSUE
DATE
VKN/AESA
VKN/AESA
ORIG. OF
CHANGE
VKN
VKN
DESCRIPTION OF CHANGE
New Data Sheet
Removed t
Updated Logic block diagram for x18 and x36 parts
Converted from preliminary to final
Updated I
Changed DLL minimum operating frequency from 80MHz to 120MHz
Changed t
Minor Change-Moved to the external web
DD
CYC
SD
/I
Revised March 10, 2008
SB
footnote
max spec to 8.4ns
specs
CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
Page 26 of 26
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