LH28F320S3NS-L11 Sharp Microelectronics, LH28F320S3NS-L11 Datasheet - Page 23

• Manufacturer Part Number: LH28F320S3NS-L11
• Description: IC FLASH 32MBIT 110NS 56SSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F320S3NS-L11

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 110ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 56-SSOP
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 425-1844; LHF32K01

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4.14 STS Configuration Command
The Status (STS) pin can be configured to different
states using the STS Configuration command. Once
the STS pin has been configured, it remains in that
configuration until another configuration command is
issued, the device is powered down or RP# is set to
V
deep power-down mode, the STS pin defaults to
RY/BY# operation where STS low indicates that the
WSM is busy. STS High Z indicates that the WSM is
ready for a new operation.
To reconfigure the STS pin to other modes, the STS
Configuration is issued followed by the appropriate
configuration code. The three alternate configurations
are all pulse mode for use as a system interrupt. The
STS Configuration command functions independently
of the V
Block Erase,
(Multi) Word/Byte
Write
Full Chip Erase
Set Block Lock-Bit
Clear Block Lock-Bits
IL
. Upon initial device power-up and after exit from
Operation
PP
voltage and RP# must be V
Lock-Bit
Block
0,1
X
X
X
0
1
Table 13. Write Protection Alternatives
V
IH
IL
WP#
.
V
V
V
V
V
V
V
V
or V
IH
IH
IH
IH
IL
IL
IL
IL
IH
Block Erase and (Multi) Word/Byte Write Enabled
Block is Locked. Block Erase and (Multi) Word/Byte Write
Disabled
Block Lock-Bit Override. Block Erase and (Multi) Word/Byte
Write Enabled
All unlocked blocks are erased, locked blocks are not erased
All blocks are erased
Set Block Lock-Bit Disabled
Set Block Lock-Bit Enabled
Clear Block Lock-Bits Disabled
Clear Block Lock-Bits Enabled
LHF32K01
Table 12. STS Configuration Coding Description
Configuration
Bits
00H
01H
02H
03H
Set STS pin to default level mode
(RY/BY#). RY/BY# in the default
level-mode of operation will indicate
WSM status condition.
Set STS pin to pulsed output signal
for specific erase operation. In this
mode, STS provides low pulse at
the completion of BLock Erase,
Full Chip Erase and Clear Block
Lock-bits operations.
Set STS pin to pulsed output signal
for a specific write operation. In this
mode, STS provides low pulse at
the completion of (Multi) Byte Write
and Set Block Lock-bit operation.
Set STS pin to pulsed output signal
for specific write and erase
operation. STS provides low pulse
at the completion of Block Erase,
Full Chip Erase, (Multi) Word/Byte
Write and Block Lock-bit
Configuration operations.
Effect
Effects
Rev. 1.55
20