LH28F320S3NS-L11 Sharp Microelectronics, LH28F320S3NS-L11 Datasheet - Page 12

• Manufacturer Part Number: LH28F320S3NS-L11
• Description: IC FLASH 32MBIT 110NS 56SSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F320S3NS-L11

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 110ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 56-SSOP
• Lead Free Status / RoHS Status: Contains lead / Request inventory verification
• Other names: 425-1844; LHF32K01

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3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer code, device code, block status codes
for each block (see Figure 4). Using the manufacturer
and device codes, the system CPU can automatically
match the device with its proper algorithms. The
block status codes identify locked or unlocked block
setting and erase completed or erase uncompleted
condition.
Figure 4. Device Identifier Code Memory Map
3FFFFF
3EFFFF
01FFFF
00FFFF
3F0006
3F0005
3F0004
3F0003
3F0000
020000
010006
010005
010004
010003
010000
000006
000005
000004
000003
000002
000001
000000
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
(Blocks 2 through 62)
Block 63 Status Code
Block 0 Status Code
Block 1 Status Code
Manufacturer Code
Device Code
Reserved for
Reserved for
Reserved for
Reserved for
Reserved for
Block 63
Block 1
Block 0
LHF32K01
3.6 Query Operation
The query operation outputs the query structure.
Query database is stored in the 48Byte ROM. Query
structure allows system software to gain critical
information for controlling the flash component.
Query structure are always presented on the lowest-
order data output (DQ
3.7 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V
controls block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Word/byte Write command requires the
command and address of the location to be written.
Set Block Lock-Bit command requires the command
and block address within the device (Block Lock) to
be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 19 and 20 illustrate
WE# and CE#-controlled write operations.
4 COMMAND DEFINITIONS
When the V
the status register, identifier codes, query, or blocks
are enabled. Placing V
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
CC
=V
CC1/2
PP
and V
voltage ≤ V
PP
=V
0
-DQ
PPH1/2/3
PPLK,
PPH1/2/3
7
) only.
Read operations from
, the CUI additionally
on V
PP
Rev. 1.55
enables
9