71321LA20PF IDT, 71321LA20PF Datasheet
71321LA20PF
Specifications of 71321LA20PF
Related parts for 71321LA20PF
71321LA20PF Summary of contents
Page 1
... OE L R/W L (2) INT L NOTES: 1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω. IDT71421 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270Ω. ©2008 Integrated Device Technology, Inc. HIGH SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ...
Page 2
... The IDT71321/IDT71421 are high-speed Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a stand-alone 8-bit Dual- Port Static RAM "MASTER" Dual-Port Static RAM together with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width systems ...
Page 3
... Industrial Symbol -0 GND -55 to +125 -65 to +150 o C NOTES (min.) = -1.5V for pulse width less than 10ns TERM 2691 tbl 01 > 10%. TERM CC 6.42 3 Industrial and Commercial Temperature Ranges Ambient GND Temperature ...
Page 4
... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE and CE I Dynamic Operating CC L Current Outputs Disabled (2) (Both Ports Active MAX I Standby Current CE and CE SB1 L (2) ...
Page 5
... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (V Symbol Parameter ( Input Leakage Current LI ( Output Leakage Current LO V Output Low Voltage (I/O -I Open Drain Output V OL Low Voltage (BUSY/INT) ...
Page 6
... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 775Ω Figure 1. AC Output Test Load BUSY or INT Figure 3. BUSY and INT AC Output Test Load GND to 3 ...
Page 7
... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time AOE ...
Page 8
... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Timing Waveform of Read Cycle No. 1, Either Side ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT NOTES and Address is valid prior to the coincidental with CE transition LOW ...
Page 9
... WC BAA LOW during a R/W controlled write cycle, the write pulse width must be the larger HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short placed on the bus for the required t ...
Page 10
... This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2 LOW during a R/W controlled write cycle, the write pulse width must be the larger HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short ...
Page 11
... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (For MASTER 71321) BUSY Access Time from Address t BAA BUSY Disable Time from Address t BDA BUSY Access Time from Chip Enable ...
Page 12
... Timing Waveform of Write with BUSY R/W "A" BUSY "B" R/W "B" NOTES: must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master BUSY is asserted on port "B" blocking R/W "B" only for the slave version (IDT71421 All timing is the same for the left and right ports. Port " ...
Page 13
... All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT71321 only). ...
Page 14
... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). ...
Page 15
... L MATCH (2) NOTES: 1. Pins BUSY and BUSY are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSY L R pull outputs. On slaves the BUSY input internally inhibits writes 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address is not met, either BUSY and enable inputs of this port ...
Page 16
... BUSY signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs the BUSY pin is an output if the part is Master (IDT71321), and the BUSY pin is an input if the part is a Slave (IDT71421) as shown in Figure ...
Page 17
... Page 4 Page 16 Page 4 Page 7 and 9 Page 17 01/17/06: Page 1 Page 17 Page 1 & 17 08/25/06: Page 14 10/29/08: Page 17 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc Process/ Temperature Range BLANK I (1) ( ...