BR24L02-W Rohm Semiconductor, BR24L02-W Datasheet - Page 25

• Manufacturer Part Number: BR24L02-W
• Description: IC EEPROM 2KBIT 400KHZ 8DIP
• Manufacturer: Rohm Semiconductor

Specifications of BR24L02-W

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 2K (256 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

●Read Command
○Read cycle
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address data
・In random read cycle, data of designated word address can be read.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential read
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when to
verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read
in succession.
cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
can be read in succession.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H'
to ACK signal after D0, and to start SDA at SCL signal 'H'.
'H'.
SDA
LINE
SDA
LINE
S D A
L IN E
S D A
L IN E
S
T
A
R
T
S
A
R
T
T
S
T
A
R
T
R
S
T
A
T
1 0
1 0
1 0
1 0
ADDRESS
A D D R E S S
ADDRESS
Fig.40 Random read cycle (BR24S16-W)
Fig.41 Random read cycle (BR24S32/64/128/256-W)
Fig.42 Current read cycle
Fig.43 Sequential read cycle (in the case of current read cycle)
N o te)
SLAVE
A D D R E S S
SLAVE
1
S L A V E
Note ）
1
1
Note )
S LA V E
0
0
1
0
A2
N ote )
A2
A 2
A1
0
A1
A 1
A0
A 2
A0
A 0
W
R
/
W
A 1
Vcc -
Note)
R
T
E
I
D
W
R
E
A
R
/
W
W
A
C
K
R
R
T
E
A 0
I
/
＊
A
C
K
A
C
K
W
WA
14
R
E
A
D
R
ADDRESS（ｎ）
/
D7
W A
1st WORD
WA
7
13
A
C
K
WA
Fig.44 Difference of slave address of each type
A D D R E S S (n)
12
*1
D 7
WA
DATA(n)
11
W O R D
D A TA (n )
1 0
A
C
K
W A
D0
0
ADDRESS（ｎ）
2nd WORD
A
C
K
A
C
K
1
S
T
A
R
T
D 0
1 0
A
C
K
0
A D D R E S S
O
S
T
P
S LA V E
1
WA
0
*1 *2 *3
A2
0
A
C
K
A 2
S
T
A
R
T
A 1
A1
1 0
A 0
ADDRESS
SLAVE
W
A
C
K
R
E
A
D
R
A0
/
1
D7
0
A
C
K
A2A1
D 7
25/32
DATA(n+x)
A0
W
R
/
R
E
A
D
D A TA (n)
A
C
K
D7
DATA(n)
D0
D 0
C
A
K
*1 BR24S16-W A2 becomes P2.
*2 BR24S16-W A1 becomes P1.
*3 BR24S16-W A0 becomes P0.
C
S
T
O
P
A
K
S
T
O
P
D0
A
C
K
O
P
S
T
*1 As for WA12, BR24S32-W become Don't care.
It is necessary to input 'H'
to the last ACK.
As for WA13, BR24S32/64-W become Don't care.
As for WA14, R24S32/64/128-W become Don't care.
It is necessary to input 'H'
to the last ACK.