BR24L02-W Rohm Semiconductor, BR24L02-W Datasheet - Page 12

IC EEPROM 2KBIT 400KHZ 8DIP

BR24L02-W

Manufacturer Part Number
BR24L02-W
Description
IC EEPROM 2KBIT 400KHZ 8DIP
Manufacturer
Rohm Semiconductor
Datasheet

Specifications of BR24L02-W

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
2K (256 x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
BR24L02-W
Manufacturer:
ROHM/罗姆
Quantity:
20 000
●WP valid timing (write cancel)
●Command cancel by start condition and stop condition
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid
timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write
cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page
write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.50.) After
execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Fig. 51.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SDA
Fig.51 Case of cancel by start, stop condition during slave address input
WP
SDA
SCL
S
T
A
R
T
SDA
SCL
Slave
address
・Rise of D0 taken clock
A
C
K
L
Enlarged view
WP cancel invalid area
Word
address
D1
C
A
K
L
D0
1
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Fig.50 WP valid timing
0
1
12/32
WP cancel valid area
A
C
K
L
Data is not written.
0
SCL
SDA
Data
Start condition
D0
Enlarged view
C
A
K
L
・Rise of SDA
ACK
S
O
P
T
Data not guaranteed
Write forced end
Stop condition
tWR

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