7132LA20JG IDT, 7132LA20JG Datasheet - Page 8

• Manufacturer Part Number: 7132LA20JG
• Description: SRAM
• Manufacturer: IDT
• Series: IDT7132SA/LAr
• Type: Dual Port RAMr

Specifications of 7132LA20JG

• Product Category: SRAM
• Rohs: yes
• Memory Size: 16 Kbit
• Organization: 2 K x 8
• Access Time: 20 ns
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Current: 200 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-52
• Interface: TTL
• Memory Type: Asynchronous
• Part # Aliases: IDT7132LA20JG

Timing Waveform of Read Cycle No. 1, Either Side
Timing Waveform of Read Cycle No. 2, Either Side
CURRENT
NOTES:
1. R/W = V
2. t
3. Start of valid data depends on which timing becomes effective last t
4. Timing depends on which signal is asserted last, OE or CE.
5. Timing depends on which signal is de-asserted first, OE or CE.
ADDRESS
DATA
BUSY
DATA
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
no relationship to valid output data.
BDD
OUT
OUT
delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has
OUT
OE
I
CE
I
CC
SS
IH,
CE = V
PREVIOUS DATA VALID
IL,
and is OE = V
IL.
Address is valid prior to the coincidental with CE transition LOW.
t
OH
t
t
AA
PU
50%
t
LZ
(4)
t
t
ACE
RC
AOE
t
, t
t
BDDH
LZ
ACE
t
AOE
(4)
,
t
AA
(2,3)
(3)
, and
8
t
BDD
.
DATA VALID
Military, Industrial and Commercial Temperature Ranges
VALID DATA
(1)
(1)
t
OH
t
t
PD
HZ
(3)
(5)
t
HZ
50%
(5)
2692 drw 08
2692 drw 07