7132LA20JG IDT, 7132LA20JG Datasheet - Page 14

• Manufacturer Part Number: 7132LA20JG
• Description: SRAM
• Manufacturer: IDT
• Series: IDT7132SA/LAr
• Type: Dual Port RAMr

Specifications of 7132LA20JG

• Product Category: SRAM
• Rohs: yes
• Memory Size: 16 Kbit
• Organization: 2 K x 8
• Access Time: 20 ns
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V
• Maximum Operating Current: 200 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-52
• Interface: TTL
• Memory Type: Asynchronous
• Part # Aliases: IDT7132LA20JG

Table II — Address BUSY
Arbitration
NOTES:
1. Pins BUSY
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
3. Writes to the left port are internally ignored when BUSY
Functional Description
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7132/IDT7142 has an
automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE =
access to the entire memory array is permitted.
Busy Logic
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a busy indication, the write
signal is gated internally to prevent the write from proceeding.
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation.
CE
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
X
X
H
L
IDT7142 (slave). BUSY
outputs. On slaves the BUSY
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If t
result. BUSY
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSY
the pin.
The IDT7132/IDT7142 provides two ports with separate control,
Busy Logic provides a hardware indication that both ports of the
The use of BUSY Logic is not required or desirable for all applica-
L
CE
X
X
H
L
R
Inputs
L
and BUSY
L
and BUSY
NO MATCH
A
A
MATCH
MATCH
MATCH
OR
OL
R
-A
-A
outputs are driving LOW regardless of actual logic level on
R
X
10L
10R
are both outputs for IDT7132 (master). Both are inputs for
R
outputs on the IDT7132 are open drain, not push-pull
outputs can not be LOW simultaneously.
APS
X
input internally inhibits writes.
is not met, either BUSY
BUSY
(2)
H
H
H
L
Outputs
(1)
V
IH
BUSY
). When a port is enabled,
(2)
H
H
H
R
L
(1)
outputs are driving LOW
L
or BUSY
Write Inhibit
Function
Normal
Normal
Normal
R
= LOW will
2692 tbl 13
(3)
14
outputs and require open drain resistors to operate. If these RAMs are
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
one master part is used to decide which side of the SRAM array will
receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master,
use the BUSY signal as a write inhibit signal. Thus on the IDT7132/
IDT7142 SRAMs the BUSY pin is an output if the part is Master (IDT7132),
and the BUSY pin is an input if the part is a Slave (IDT7142) as shown
in Figure 3.
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
270Ω
BUSY
The BUSY outputs on the IDT7132 RAM master are open drain type
When expanding an SRAM array in width while using BUSY logic,
If two or more master parts were used when expanding in width, a
The BUSY arbitration, on a Master, is based on the chip enable and
5V
Figure 4. Busy and chip enable routing for both width and depth
L
Military, Industrial and Commercial Temperature Ranges
expansion with IDT7132 (Master) and (Slave) IDT7142 SRAMs.
MASTER
Dual Port
SRAM
BUSY
MASTER
Dual Port
SRAM
BUSY
L
L
BUSY
BUSY
CE
CE
R
R
SLAVE
Dual Port
SRAM
BUSY
SLAVE
Dual Port
SRAM
BUSY
L
L
BUSY
BUSY
CE
CE
R
R
2692 drw 15
BUSY
5V
R
270Ω