7132LA20JG IDT, 7132LA20JG Datasheet - Page 12

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7132LA20JG

Manufacturer Part Number
7132LA20JG
Description
SRAM
Manufacturer
IDT
Series
IDT7132SA/LAr
Type
Dual Port RAMr
Datasheet

Specifications of 7132LA20JG

Product Category
SRAM
Rohs
yes
Memory Size
16 Kbit
Organization
2 K x 8
Access Time
20 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Current
200 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
PLCC-52
Interface
TTL
Memory Type
Asynchronous
Part # Aliases
IDT7132LA20JG
Timing Waveform of Write with Port-to-Port Read and BUSY
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
DATA
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
DATA
ADDR
BUSY
WB
WH
ADDR
R/W
L
OUT"B"
applies only to the slave version (IDT7142).
must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
= CE
IN"A"
IL
"A"
"B"
"B"
"A"
for the reading port.
R
= V
IL
BUSY
R/W
R/W
"B"
"B"
"A"
t
APS
"B"
(1)
, until BUSY
APS
is ignored for Slave (IDT7142).
"B"
goes HIGH.
t
BAA
t
WB
(3)
MATCH
t
WC
(2)
12
t
WP
(4)
t
WP
Military, Industrial and Commercial Temperature Ranges
MATCH
VALID
t
DW
t
t
t
WDD
WH
BDA
2692 drw 12
(1)
t
DDD
t
DH
t
BDD
,
(2,3,4)
VALID
2692 drw 11

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