7132LA20JG IDT, 7132LA20JG Datasheet

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7132LA20JG

Manufacturer Part Number
7132LA20JG
Description
SRAM
Manufacturer
IDT
Series
IDT7132SA/LAr
Type
Dual Port RAMr
Datasheet

Specifications of 7132LA20JG

Product Category
SRAM
Rohs
yes
Memory Size
16 Kbit
Organization
2 K x 8
Access Time
20 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
4.5 V
Maximum Operating Current
200 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
PLCC-52
Interface
TTL
Memory Type
Asynchronous
Part # Aliases
IDT7132LA20JG
Features
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
NOTES:
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
2. Open drain output: requires pullup resistor of 270Ω.
Functional Block Diagram
©2010 Integrated Device Technology, Inc.
I/O
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7132/42SA
– IDT7132/42LA
IDT7142 (SLAVE): BUSY is input.
BUSY
OL-
Active: 325mW (typ.)
Standby: 5mW (typ.)
Active: 325mW (typ.)
Standby: 1mW (typ.)
R/W
I/O
A
OE
CE
A
10L
7L
L
0L
L
L
L
(1,2)
Decoder
Address
R/W
OE
CE
L
L
L
11
Control
I/O
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
ARBITRATION
MEMORY
ARRAY
LOGIC
1
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
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MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
On-chip port arbitration logic (IDT7132 only)
BUSY output flag on IDT7132; BUSY input on IDT7142
Battery backup operation —2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Control
I/O
11
Decoder
Address
CE
OE
R/W
R
R
R
SEPTMEBER 2010
2692 drw 01
IDT7132SA/LA
IDT7142SA/LA
OE
CE
R/W
I/O
BUSY
A
A
10R
0R
OR-
R
R
R
DSC-2692/19
I/O
R
(1,2)
7R
m

Related parts for 7132LA20JG

7132LA20JG Summary of contents

Page 1

... R/W L NOTES: 1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω. IDT7142 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor of 270Ω. ©2010 Integrated Device Technology, Inc. HIGH SPEED DUAL PORT STATIC RAM ◆ ◆ ◆ ◆ ◆ ...

Page 2

... High Speed Dual Port Static RAM Description The IDT7132/IDT7142 are high-speed Dual-Port Static RAMs. The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM “MASTER” Dual-Port RAM together with the IDT7142 “SLAVE” Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/ ...

Page 3

... Recommended DC Operating Conditions Symbol V Supply Voltage CC > Vcc + 10%. TERM GND Ground V Input High Voltage IH V Input Low Voltage IL NOTES (min.) = -1.5V for pulse width less than 10ns must not exceed Vcc + 10%. TERM 3 6. ...

Page 4

... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE I Dynamic Operating Current CC (Both Ports Active) Outputs Disabled Standby Current SB1 (Both Ports - TTL Level Inputs) ...

Page 5

... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL Open Drain Output V OL Low Voltage (BUSY) ...

Page 6

... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V DATA OUT 775Ω *100pF for 55 and 100ns versions Figure 1. AC Output Test Load ...

Page 7

... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time ...

Page 8

... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM Timing Waveform of Read Cycle No. 1, Either Side ADDRESS t OH DATA PREVIOUS DATA VALID OUT BUSY OUT Timing Waveform of Read Cycle No. 2, Either Side CE OE DATA OUT I CC CURRENT I SS NOTES: ...

Page 9

... WC BAA LOW during a R/W controlled write cycle, the write pulse width must be the larger High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t bus for the required ...

Page 10

... This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2 LOW during a R/W controlled write cycle, the write pulse width must be the larger HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t ...

Page 11

... WH t Write Data Valid to Read Data Delay DDD (3) t Arbitration Priority Set-up Time APS BUSY Disable to Valid Data (4) t BDD BUSY Timing (For Slave IDT7142 Only) Write to BUSY Input ( Write Hold After BUSY ( (2) t Write Pulse to Data Delay WDD ...

Page 12

... Timing Waveform of Write with BUSY R/W "A" BUSY "B" R/W "B" NOTES: must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master BUSY is asserted on port "B" blocking R/W "B" applies only to the slave version (IDT7142 All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port " ...

Page 13

... IDT7132SA/LA and IDT 7142SA/LA High Speed Dual Port Static RAM Timing Waveform of BUSY Arbitration Controlled by CE Timing ADDR and "A" "B" CE "B" (2) t APS CE "A" BUSY "A" Timing Waveform of BUSY Arbitration Controlled by Address Match Timing ...

Page 14

... BUSY signal as a write inhibit signal. Thus on the IDT7132/ 2692 tbl 13 IDT7142 SRAMs the BUSY pin is an output if the part is Master (IDT7132), and the BUSY pin is an input if the part is a Slave (IDT7142) as shown in Figure 3. or BUSY = LOW will ...

Page 15

... Commercial & Military LA Low Power SA Standard Power 7132 16K (2K x 8-Bit) MASTER Dual-Port RAM 7142 16K (2K x 8-Bit) SLAVE Dual-Port RAM Changed drawing format Changed Busy Logic and Width Expansion copy parameter A 15 6.42 , ⎫ ⎬ Speed in nanoseconds ⎭ 2692 drw 16 ...

Page 16

... Page 14 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Military, Industrial and Commercial Temperature Ranges Corrected errors in Figure 3 by changing 1250 Clarified Industrial temp offering for 25ns Removed INT from V ...

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