92HD90B0X5NLGXYAX IDT, 92HD90B0X5NLGXYAX Datasheet - Page 67
92HD90B0X5NLGXYAX
Manufacturer Part Number
92HD90B0X5NLGXYAX
Description
Interface - CODECs
Manufacturer
IDT
Datasheet
1.92HD90B0X5NLGXYAX8.pdf
(303 pages)
Specifications of 92HD90B0X5NLGXYAX
Rohs
yes
Part # Aliases
IDT92HD90B0X5NLGXYAX
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92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
Field Name
Mask4
Mask3
Mask2
Mask1
Mask0
Field Name
Rsvd
Control4
Control3
Reg
Get
Set
7.4.13. AFG (NID = 01h): GPIODir
Byte 4 (Bits 31:24)
Bits
4
Enable for GPIO4: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
3
Enable for GPIO3: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
2
Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
1
Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
0
Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior
determined by GPIO Direction control
Bits
31:5
Reserved.
4
Direction control for GPIO4: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
3
Direction control for GPIO3: 0 = GPIO is configured as input; 1 = GPIO is con-
figured as output
Byte 3 (Bits 23:16)
R/W
RW
RW
RW
RW
RW
R/W
R
RW
RW
F1700h
Default
0h
0h
0h
0h
0h
Default
00000000h
0h
0h
62
Byte 2 (Bits 15:8)
Reset
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
Byte 1 (Bits 7:0)
717h
V 1.2 3/12
92HD98
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