92HD90B0X5NLGXYAX IDT, 92HD90B0X5NLGXYAX Datasheet - Page 64
92HD90B0X5NLGXYAX
Manufacturer Part Number
92HD90B0X5NLGXYAX
Description
Interface - CODECs
Manufacturer
IDT
Datasheet
1.92HD90B0X5NLGXYAX8.pdf
(303 pages)
Specifications of 92HD90B0X5NLGXYAX
Rohs
yes
Part # Aliases
IDT92HD90B0X5NLGXYAX
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92HD98
SINGLE CHIP PC AUDIO SYSTEM, CODEC+MONO SPEAKER AMPLIFIER+CAPLESS HP+LDO
IDT CONFIDENTIAL
©2009 INTEGRATED DEVICE TECHNOLOGY, INC.
Field Name
Rsvd3
StepSize
Rsvd2
NumSteps
Rsvd1
Offset
Field Name
Rsvd3
SettingsReset
ClkStopOK
Error
Reg
Get
Set
7.4.9.
Byte 4 (Bits 31:24)
AFG (NID = 01h): PwrState
Bits
30:23
Reserved.
22:16
Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.
15
Reserved.
14:8
Number of gains steps (number of possible settings - 1).
7
Reserved.
6:0
Indicates which step is 0dB
Bits
31:11
Reserved.
10
Indicates if any persistent settings in this Function Group have been reset.
Cleared by PwrState 'Get' to this Widget.
9
Bit clock can currently be removed: 1 = yes, 0 = no.
8
Error indicator: 1 = cannot enter requested power state, 0 = no problem with
requested power state.
Byte 3 (Bits 23:16)
R/W
R
R
R
R
R
R
R/W
R
R
R
R
F0500h
Default
00h
02h
0h
7Fh
0h
7Fh
Default
000000h
1h
1h
0h
59
Byte 2 (Bits 15:8)
Reset
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
N/A (Hard-coded)
Reset
N/A (Hard-coded)
POR - DAFG - ULR
POR - DAFG - ULR
POR - DAFG - ULR
Byte 1 (Bits 7:0)
705h
V 1.2 3/12
92HD98
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