LPC1114FHN33/203,5 NXP Semiconductors, LPC1114FHN33/203,5 Datasheet - Page 492
LPC1114FHN33/203,5
Manufacturer Part Number
LPC1114FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 32 kB Fl 8 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1114FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1114
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
32 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
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NXP Semiconductors
UM10398
User manual
28.5.7.4.4 Condition flags
28.5.7.4.5 Examples
28.5.7.5.1 Syntax
28.5.7.5.2 Operation
28.5.7.5.3 Restrictions
28.5.7.5.4 Condition flags
28.5.7.5.5 Examples
28.5.7.6.1 Syntax
28.5.7.6.2 Operation
28.5.7.6.3 Restrictions
28.5.7.5 ISB
28.5.7.6 MRS
This instruction does not change the flags.
Instruction Synchronization Barrier.
ISB
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
so that all instructions following the ISB are fetched from cache or memory again, after the
ISB instruction has been completed.
There are no restrictions.
This instruction does not change the flags.
Move the contents of a special register to a general-purpose register.
MRS Rd, spec_reg
where:
MRS stores the contents of a special-purpose register to a general-purpose register. The
MRS instruction can be combined with the MR instruction to produce read-modify-write
sequences, which are suitable for modifying a specific flag in the PSR.
See
In this instruction, Rd must not be SP or PC.
DSB ; Data Synchronisation Barrier
ISB ; Instruction Synchronisation Barrier
Rd is the general-purpose destination register.
spec_reg is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR, IAPSR,
EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
Section
28–28.5.7.7.
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
UM10398
© NXP B.V. 2012. All rights reserved.
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