MAX110BCAP+ Maxim Integrated, MAX110BCAP+ Datasheet - Page 10
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MAX110BCAP+
Manufacturer Part Number
MAX110BCAP+
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet
1.MAX111AEAP-T.pdf
(24 pages)
Specifications of MAX110BCAP+
Number Of Channels
2
Architecture
Sigma-Delta
Conversion Rate
0.05 KSPs
Resolution
14 bit
Input Type
Single-Ended/Differential
Snr
No
Interface Type
QSPI, Serial (SPI, Microwire)
Operating Supply Voltage
+/- 5V
Maximum Operating Temperature
+ 70 C
Package / Case
SSOP-20
Maximum Power Dissipation
842 mW
Minimum Operating Temperature
0 C
Number Of Converters
1
Voltage Reference
5.3 V
XCLK internally connects to a clock-frequency divider
network, whose output is the ADC oversampling clock,
f
oscillator or external clock applied to XCLK) to be
divided by one, two, or four (see Clock Divider-Ratio
Control Bits ).
Figure 3 shows the two methods for providing the over-
sampling clock to the MAX110/MAX111. In external-
clock mode (Figure 3a), the internal RC oscillator is
disabled and XCLK accepts a TTL/CMOS-level clock to
provide the oversampling clock to the ADC.
Select external-clock mode (Figure 3a) by connecting
RCSEL to GND and a TTL/CMOS-compatible clock to
XCLK (see Selecting the Oversampling Clock
Frequency ).
In RC-oscillator mode (Figure 3b), the internal RC oscil-
lator is active and its output is connected to XCLK
(Figure 1). Select RC-oscillator mode by connecting
RCSEL to V
connects it to XCLK for use by the ADC and external
system components. Minimize the capacitive loading on
XCLK when using the internal RC oscillator.
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
Figure 1. Functional Diagram
10
OSC
. This allows the selected clock source (internal RC
______________________________________________________________________________________
DD
IN1+
IN1-
IN2+
IN2-
REF+
REF-
. This enables the internal oscillator and
INPUT
MUX
IN+
IN-
Oversampling Clock
MAX110
MAX111
Gm
Gm
GENERATOR
DITHER
-
INTEGRATOR
Figure 2. ADC Waveforms During a Conversion
OVERSAMPLING
OUTPUT FROM
DIFFERENTIAL
1-BIT DAC
ANALOG
CLOCK
INPUT
V
V
V
V
REF+
REF-
REF+
REF-
UP/DOWN
COUNTER
LOGIC + CLOCK GENERATOR
DC LEVEL AT 1/2 V
TIMER + CONTROL
OSCILLATOR
NETWORK,
DIVIDE BY
1, 2, OR 4
DIVIDER
DIN
RC
OSC
SCLK CS
REGISTER
CONTROL
REGISTER
REF
SERIAL
SHIFT
16
16
16
16
DOUT
BUSY
RCSEL
XCLK
MAX110
MAX111