MC9S12P64VQK Freescale Semiconductor, MC9S12P64VQK Datasheet - Page 306
MC9S12P64VQK
Manufacturer Part Number
MC9S12P64VQK
Description
16-bit Microcontrollers - MCU 16 BIT 64K FLASH
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12P64VQK.pdf
(566 pages)
Specifications of MC9S12P64VQK
Rohs
yes
Core
S12
Processor Series
MC9S12P
Data Bus Width
16 bit
Maximum Clock Frequency
64 MHz
Program Memory Size
64 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
5 V
Operating Temperature Range
- 40 C to 105 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Interface Type
I2C, SCI, SPI
Program Memory Type
Flash
Available stocks
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Analog-to-Digital Converter (ADC12B10C)
9.1.2
9.1.2.1
There is software programmable selection between performing single or continuous conversion on a
single channel or multiple channels.
9.1.2.2
306
•
•
•
•
•
Configurable external trigger functionality on any AD channel or any of four additional trigger
inputs. The four additional trigger inputs can be chip external or internal. Refer to device
specification for availability and connectivity.
Configurable location for channel wrap around (when converting multiple channels in a sequence).
Stop Mode
— ICLKSTP=0 (in ATDCTL2 register)
— ICLKSTP=1 (in ATDCTL2 register)
Wait Mode
ADC12B10C behaves same in Run and Wait Mode. For reduced power consumption continuous
conversions should be aborted before entering Wait mode.
Freeze Mode
In Freeze Mode the ADC12B10C will either continue or finish or stop converting according to the
FRZ1 and FRZ0 bits. This is useful for debugging and emulation.
Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted
restarts it after exiting stop mode. This has the same effect/consequences as starting a
conversion sequence with write to ATDCTL5. So after exiting from stop mode with a
previously aborted sequence all flags are cleared etc.
A/D conversion sequence seamless continues in Stop Mode based on the internally generated
clock ICLK as ATD clock. For conversions during transition from Run to Stop Mode or vice
versa the result is not written to the results register, no CCF flag is set and no compare is done.
When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time
required to switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access
ATD registers during
Modes of Operation
Conversion Modes
MCU Operating Modes
this time
S12P-Family Reference Manual, Rev. 1.13
.
Freescale Semiconductor
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ATDSTPRCV
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