AS4C8M16S-7BCNTR Alliance Memory, AS4C8M16S-7BCNTR Datasheet - Page 50
![no-image](/images/no-image-200.jpg)
AS4C8M16S-7BCNTR
Manufacturer Part Number
AS4C8M16S-7BCNTR
Description
DRAM 128Mb, 3.3V, 143Mhz 8M x 16 SDRAM
Manufacturer
Alliance Memory
Datasheet
1.AS4C8M16S-7BCN.pdf
(53 pages)
Specifications of AS4C8M16S-7BCNTR
Rohs
yes
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Figure 41. Full Page Random Column Write
Figure 42. Precharge Termination of a Burst
A0-A9,
A11
BA0,1
CKE
WE#
DQM
CLK
RAS#
CAS#
CKE
CS#
RAS#
CAS#
WE#
BA0,1
CLK
A10
A0-A9,
A11
DQM
DQ
FEBRUARY 2011
Activate
Cammand
Bank A
High
Hi-Z
RAx
RAx
T0
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
Cammand Command
Activate
Bank A
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
RAx
RAx
t
RRD
Write
Command
Bank A
Activate
Bank B
DAx0 DAx1
CAx
RBx
RBx CAx
Precharge Termination
of a Write Burst
Write Data are masked
Write
Command
Bank A
DAx0 DAx1 DBx0 DAy0
t
RCD
t
WR
Write
Command
Bank B
Precharge
Command
Bank A
CBx CAy
t
RP
Write
Command
Bank A
DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Activate
Command
Bank A
Write
Command Command
Bank B
RAy
RAy
CBy
50
Write
Bank A
CAz
(Burst Length=Full Page)
CAy
Read
Command
Bank A
Write
Command
Bank B
CBz
Precharge
Command
Bank A
Ay0 Ay1
t
RP
Write Data
are masked
t
WR
Ay2
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank A
RAz
RAz
Don’t Care
t
RP
Precharge Termination
of a Read Burst
AS4C8M16S
RBw
Activate
Command
Bank B
RBw
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