AS4C8M16S-7BCNTR Alliance Memory, AS4C8M16S-7BCNTR Datasheet - Page 5

• Manufacturer Part Number: AS4C8M16S-7BCNTR
• Description: DRAM 128Mb, 3.3V, 143Mhz 8M x 16 SDRAM
• Manufacturer: Alliance Memory

Specifications of AS4C8M16S-7BCNTR

• Rohs: yes

BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Clock Suspend Mode Entry
Power Down Mode Entry
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Operation Mode
Table 4 shows the truth table for the operation commands.
Note: 1. V=Valid, X=Don't Care L=Low level H=High level
FEBRUARY 2011
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
2. CKE
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode cannot enter in the burst operation.
Command State
CKE
When this command is asserted in the burst cycle, device state is clock suspend mode.
n-1
n
signal is input level when commands are provided.
signal is input level one clock cycle before the commands are provided.
(PowerDown)
(SelfRefresh)
Active
Active
Active
Active
Active
Active
Active
Active
Active
Idle
Any
Any
Any
Idle
Any
Any
Idle
Idle
Idle
Any
Table 4. Truth Table (Note (1), (2))
(3)
(5)
(3)
(3)
(3)
(3)
(4)
CKE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
n-1
CKE
X
X
X
X
X
X
H
H
H
H
X
X
X
X
X
X
X
L
L
L
n
5
DQM BA
H
X
X
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
L
V
V
X
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
0,1
OP code
A
Row address
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
10
(A0 ~ A8)
(A0 ~ A8)
A
address
address
Column
Column
0-9,11
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CS# RAS# CAS# WE#
H
H
H
H
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
X
X
H
X
V
X
H
X
X
H
X
X
L
L
L
L
L
L
AS4C8M16S
H
H
H
H
H
X
X
H
X
V
X
H
X
X
H
X
X
L
L
L
L
L
L
L
H
H
H
H
X
H
H
X
H
X
V
X
H
X
X
H
X
X
L
L
L
L
L
L