IS46R16160D-6BLA2 ISSI, IS46R16160D-6BLA2 Datasheet - Page 23

• Manufacturer Part Number: IS46R16160D-6BLA2
• Description: DRAM 256Mb, 2.5V, 166MHz 64M x 8 DDR1
• Manufacturer: ISSI

Specifications of IS46R16160D-6BLA2

• Rohs: yes
• Organization: 64 M x 8
• Package / Case: BGA-60
• Memory Size: 256 MB
• Maximum Clock Frequency: 167 MHz
• Access Time: 6 ns
• Supply Voltage - Max: 2.7 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43R83200D
IS43/46R16160D, IS43/46R32800D
IDD Specification Parameters and Test Conditions: x32
(V
Integrated Silicon Solution, Inc.
Rev. B
06/19/2012
Symbol
DD
IDD4W
IDD3N
IDD4R
IDD2P
IDD2F
IDD3P
IDD0
IDD1
IDD5
IDD6
IDD7
= V
DDq
= 2.5V ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Parameter/ Test Condition
Operating current for one bank active-precharge; tRC = tRC(min);
tCK = tCK(min); DQ, DM and DQS inputs changing once per clock
cycle; address and control inputs changing once every two clock
cycles; CS = high between valid commands.
Operating current for one bank operation; one bank open, BL = 4,
tRC = tRC(min), tCK = tCK(min), Iout=0mA, Address and control
inputs changing once per clock cycle.
Precharge power-down standby current; all banks idle; power-down
mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and
DM
Precharge floating standby current; CS VIH(min); all banks idle; CKE
VIH(min); tCK = tCK(min); address and other control inputs changing
once per clock cycle; VIN = VREF for DQ, DQS and DM
Active power-down standby current; one bank active; power-down
mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and
DM
Active standby current; CS VIH(min); CKE VIH(min); one bank
active; tRC = tRAS(max); tCK = tCK(min); DQ, DQS and DM inputs
changing twice per clock cycle; address and other control inputs
changing once per clock cycle
Operating current for burst read; burst length = 2; reads; continuous
burst; one bank active; address and control inputs changing once per
clock cycle; tCK = tCK(min); 50% of data changing on every transfer;
lOUT = 0mA
Operating current for burst write; burst length = 2; writes; continuous
burst; one bank active address and control inputs changing once per
clock cycle; tCK = tCK(min); DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every transfer
Auto refresh current; tRC = tRFC(min);
Self refresh current; CKE 0.2V;
Operating current for four bank operation; four bank interleaving
READs (BL=4) with auto precharge; tRC = tRC(min), tCK = tCK(min);
Address and control inputs change only during ACTIVE, READ, or
WRITE commands
180
190
330
340
220
460
35
65
45
80
10
-5
160
170
300
310
220
430
35
65
45
80
10
-6
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
23