IS46R16160D-6BLA2 ISSI, IS46R16160D-6BLA2 Datasheet - Page 17

• Manufacturer Part Number: IS46R16160D-6BLA2
• Description: DRAM 256Mb, 2.5V, 166MHz 64M x 8 DDR1
• Manufacturer: ISSI

Specifications of IS46R16160D-6BLA2

• Rohs: yes
• Organization: 64 M x 8
• Package / Case: BGA-60
• Memory Size: 256 MB
• Maximum Clock Frequency: 167 MHz
• Access Time: 6 ns
• Supply Voltage - Max: 2.7 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43R83200D
IS43/46R16160D, IS43/46R32800D
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is
reached.
The block is uniquely selected by A1-An when the burst length is set to two, by A2-An when the burst length is set
to 4, by A3-An when the burst length is set to 8. An is the most significant column address bit, which depends if the
device is x8, x16 or x32. An = A9 for x8, An = A8 for x16 and An = A9 for x32. The programmed burst length applies to
both read and write bursts.
BURST TYPE
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address.
READ LATENCY
The READ latency, or CAS latency, is the delay between the registration of a READ command and the availability of
the first piece of output data.
If a READ command is registered at a clock edge n and the latency is 3 clocks, the first data element will be valid at
n + 2tCK + tAC. If a READ command is registered at a clock edge n and the latency is 2 clocks, the first data element
will be valid at n + tCK + tAC.
OPERATING MODE
The normal operating mode is selected by issuing a Mode Register Set command with bits A7 to An each set to zero,
and bits A0 to A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with
bits A7 and A9 to An each set to zero, bit A8 set to one, and bits A0 to A6 set to the desired values. A Mode Register
Set command issued to reset the DLL must always be followed by a Mode Register Set command to select normal
operating mode (A8=0).
All other combinations of values for A7 to An are reserved for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or incompatibility with future versions may result.
Integrated Silicon Solution, Inc.
17
Rev. B
06/19/2012