IS49NLC36160-25EBL ISSI, IS49NLC36160-25EBL Datasheet - Page 7

• Manufacturer Part Number: IS49NLC36160-25EBL
• Description: DRAM 576M, x36, 400Mhz RLDRAM2
• Manufacturer: ISSI

Specifications of IS49NLC36160-25EBL

• Rohs: yes
• Organization: 16 M x 36
• Package / Case: FBGA-144
• Memory Size: 576 Mbit
• Maximum Clock Frequency: 400 MHz
• Access Time: 2.5 ns
• Supply Voltage - Max: 2.63 V
• Supply Voltage - Min: 2.38 V
• Maximum Operating Current: 380 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT

IS49NLC96400,IS49NLC18320,IS49NLC36160
2.4 Operating Conditions and Maximum Limits
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 12/4/2012
read current
Operational
Description
Distributed
Operating
Operating
Standby
standby
current
current
current
refresh
current
refresh
current
current
Active
Burst
burst
write
burst
Condition
t
CS# =1; No commands; Bank address incremented and
half address/data change once every 4 clock cycles
BL=2; Sequential bank access; Bank transitions once
every t
followed by write sequence; continuous data during
WRITE commands
BL = 4; Sequential bank access; Bank transitions once
every t
followed by write sequence; Continuous data during
WRITE commands
BL = 8; Sequential bank access; Bank transitions once
every t
followed by write sequence; continuous data during
WRITE commands
Eight-bank cyclic refresh; Continuous address/data;
Command bus remains in refresh for all eight banks
Single-bank refresh; Sequential bank access; Half
address transitions once every t
BL=2; Cyclic bank access; Half of address bits change
every clock cycle; Continuous data; measurement is
taken during continuous WRITE
BL=4; Cyclic bank access; Half of address bits change
every 2 clock cycles; Continuous data; Measurement is
taken during continuous WRITE
BL=8; Cyclic bank access; Half of address bits change
every 4 clock cycles; continuous data; Measurement is
taken during continuous WRITE
BL=2; Cyclic bank access; Half of address bits change
every clock cycle; Measurement is taken during
continuous READ
BL=4; Cyclic bank access; Half of address bits change
every clock cycle; Measurement is taken during
continuous READ
BL=8; Cyclic bank access; Half of address bits change
every clock cycle; Measurement is taken during
continuous READ
CK
= idle; All banks idle; No inputs toggling
RC
RC
RC
; Half address transitions once every t
; Half address transitions once every tRC; Read
; half address transitions once every tRC; Read
RC
, continuous data
RC
; Read
IDD2W(V
IDD4W(V
IDD8W(V
IDD2R(V
IDD4R(V
IDD8R(V
IDD3 (V
IREF1(V
IREF2(V
IDD1(V
IDD2(V
ISB1(V
ISB2(V
IDD2W(V
IDD4W(V
IDD8W(V
IDD2R(V
IDD4R(V
IDD8R(V
IDD3 (V
IREF1(V
IREF2(V
IDD1(V
IDD2(V
ISB1(V
ISB2(V
IDD2W(V
IDD4W(V
IDD8W(V
IDD2R(V
IDD4R(V
IDD8R(V
IREF1(V
IREF2(V
IDD1(V
IDD2(V
IDD3(V
ISB1(V
ISB2(V
Symbol
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
) x9/x18
) x9/x18
) x9/x18
) x9/x18
DD
DD
DD
) x9/x18
) x9/x18
) x9/x18
DD
DD
DD
) x9/x18
) x9/x18
) x9/x18
DD
DD
DD
) x9/x18
) x9/x18
) x9/x18
) x36
EXT
) x36
EXT
) x36
EXT
) x36
EXT
EXT
) x36
) x36
EXT
) x36
EXT
) x36
EXT
) x36
EXT
) x36
EXT
EXT
EXT
EXT
) x36
) x36
) x36
)
)
)
)
)
)
)
)
)
)
)
)
)
1105
-25E
293
293
380
400
400
425
430
540
790
915
330
390
980
785
887
675
755
940
995
685
735
575
665
53
53
15
15
20
80
20
50
30
30
50
30
30
5
5
288
288
348
374
362
418
408
460
785
785
325
326
970
990
779
882
668
750
935
990
680
730
570
660
-25
48
48
15
15
20
80
20
50
30
30
50
30
30
5
5
233
233
305
343
319
389
368
425
615
615
267
281
819
914
609
790
525
580
735
795
525
660
450
505
-33
48
48
13
13
18
70
18
40
25
25
40
25
25
5
5
189
189
255
292
269
339
286
425
430
430
221
227
597
676
439
567
364
580
525
565
380
455
310
505
48
48
13
13
18
70
18
40
25
25
40
25
25
-5
5
5
units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
7