IS46R16160D-6TLA2-TR ISSI, IS46R16160D-6TLA2-TR Datasheet - Page 15

• Manufacturer Part Number: IS46R16160D-6TLA2-TR
• Description: DRAM 256Mb, 2.5V, 166MHz 64M x 8 DDR1
• Manufacturer: ISSI

Specifications of IS46R16160D-6TLA2-TR

• Rohs: yes
• Organization: 64 M x 8
• Package / Case: TSOP-66
• Memory Size: 256 MB
• Maximum Clock Frequency: 167 MHz
• Access Time: 6 ns
• Supply Voltage - Max: 2.7 V
• Supply Voltage - Min: 2.3 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT

IS43R83200D
IS43/46R16160D, IS43/46R32800D
MODE REGISTER (MR) DEFINITION
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes
the definition of a burst length, a burst type, and a CAS latency. The Mode Register is programmed via the MODE
REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is reprogrammed,
or the device loses power. Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or
interleave), A4-A6 the CAS latency, and A8 DLL reset. A logic 0 should be programmed to all the undefined addresses
bits to ensure future compatibility. The Mode Register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating
either of these requirements will result in unspecified operation. Reserved states should not be used, as unknown
operation or incompatibility with future versions may result
Integrated Silicon Solution, Inc.
Rev. B
06/19/2012
BA1 BA0 A12
MODE REGISTER
BA1 BA0 Mode Register Definition
0
0
1
1
0
1
0
1
Program Mode Register
Program Extended Mode Register
Reserved
Reserved
A12 A11 A10 A9 A8 A7 DLL
0
0
1
0
0
A11
0
0
A10
0
0
0
1
A9
0
0
Normal operation
Reset DLL
A8
A7
A6
Notes:
1. A12 is not used in x32 and should be ignored for this option.
2. A logic 0 should be programmed to all unused / undefined
A5
A6 A5 A4 CAS Latency
0
0
0
0
1
1
1
1
address bits to ensure future compatibility.
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
2.5
Reserved
A3
A3 Burst Type
0
1
Sequential
Interleave
A2
A2 A1 A0 Burst Length
A1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Address Bus (Ax)
Mode Reg. (Ex)
15