IS46R16160D-6TLA2-TR ISSI, IS46R16160D-6TLA2-TR Datasheet

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... Industrial (-40°C to +85°C) Automotive, A1 (-40°C to +85°C) Automotive, A2 (-40°C to +105°C) Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D FUNCTIONAL BLOCK DIAGRAM ( CK COMMAND CK DECODER CKE & CS CLOCK RAS GENERATOR CAS WE Mode Registers and Ext. Mode Registers 14 A11 A10 ROW ADDRESS ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D FUNCTIONAL BLOCK DIAGRAM ( CK COMMAND CK DECODER CKE & CS CLOCK RAS GENERATOR CAS WE Mode Registers and Ext. Mode Registers A12 15 A11 A10 ROW ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D PIN CONFIGURATIONS 66 pin TSOP - Type II  for  DQ0 DQ1 DQ2 DQ3 DDQ NC NC VDD CAS RAS CS ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D PIN CONFIGURATION Package Code B: 60-ball FBGA (top view) for x8 (8mm x 13mm Body, 0.8mm Ball Pitch) Top View (Balls seen through the Package) : Ball Existing : Depopulated Ball Top View(See the balls through the Package ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D PIN CONFIGURATIONS 66 pin TSOP - Type II  for x16 V DD DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NC V DDQ LDQS NC VDD NC LDM WE CAS RAS CS ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D PIN CONFIGURATION Package Code B: 60-ball FBGA (top view) for x16 (8mm x 13mm Body, 0.8mm Ball Pitch) Top View (Balls seen through the Package) : Ball Existing : Depopulated Ball Top View(See the balls through the Package ...

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... F DQ19 DQ18 G DQS2 DM2 H DQ21 DQ20 J DQ22 DQ23 K CAS WE L RAS Note: Vss balls inside the dotted box are optional for purposes of thermal dissipation. PIN DESCRIPTION: for x32 A0-A11 Row Address Input A0-A7, A9 Column Address Input BA0, BA1 Bank Select Address DQ0 – DQ31 Data I/O CK, CK System Clock Input CKE Clock Enable CS Chip Select CAS Column Address Strobe Command RAS Row Address Strobe Command ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D PIN FUNCTIONAL DESCRIPTIONS Symbol Type Description CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Input and output data is referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are derived from CK/ CK. CKE Input Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE, are disabled during power-down and self refresh mode which are contrived for low standby power consumption. Input Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command CS decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks considered part of the command code. Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. RAS, CAS, WE DM: x8; Input Input Data Mask input mask signal for write data. Input data is masked when DM is LDM, UDM: sampled HIGH along with that input data during a WRITE access sampled on both edges x16; of DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading. DM0-DM3: For x16 devices, LDM corresponds to the data on DQ0-DQ7, UDM corresponds to the data on x32 ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D COMMANDS TRUTH TABLES All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high and CK going low). Truth Table shows basic timing parameters for all commands. TRUTH TABLE - COMMANDS NAME (FUNCTION)  DESELECT (NOP) NO OPERATION (NOP) ACTIVE (select bank and activate row) READ (select bank and column and start read burst) READ with AP (read burst with Auto Precharge) WRITE (select bank and column and start write burst) WRITE with AP (write burst with Auto Precharge) BURST TERMINATE PRECHARGE (deactivate row in selected bank) PRECHARGE ALL (deactivate rows in all banks) AUTO REFRESH or enter SELF REFRESH MODE REGISTER SET Notes: 1. All states and sequences not shown are illegal or reserved. 2. DESELECT and NOP are functionally interchangeable. 3. Autoprecharge is non-persistent. AP High enables Auto Precharge, while AP Low disables Autoprecharge. 4. Burst Terminate applies to only Read bursts with Auto Precharge disabled. This command is undefined and should not be used for Read with Auto Precharge enabled, and for Write bursts Low, bank address determines which bank precharged High, all banks are precharged and BA0- BA1are don’t care. 6. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low. ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D TRUTH TABLE - CKE CKE n-1 CKE n Current State L L Power Down L L Self Refresh L H Power Down L H Self Refresh H L All Banks Idle H L Bank(s) Active H L All Banks Idle H H Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of DDR immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is the result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D Power Applied Power On Precharge PREALL MRS EMRS Write Write A PREALL = Precharge All Banks CKEL = Enter Power Down MRS = Mode Register Set CKEH = Exit Power Down EMRS = Extended Mode Register Set ACT = Active 12 SIMPLIFIED STATE DIAGRAM REFS REFSX MRS REFA Idle CKEL CKEH Active Power ACT Down CKEH CKEL Row Active Read Write Write ...

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... Prior to normal operation, the DDR SDRAM must be initialized. The following section provides detailed information covering device initialization, register definition, command description and device operation INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. Operations procedures other than those specified may result in undefined operation. If there is any interruption to the device power, the initialization routine should be followed. The steps to be followed for device initialization are listed below. The Initialization Flow diagram and the Initialization Flow sequence are shown in the following figures ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D Initialization Waveform Sequence VDD tVDT≥ 0 VDDQ VTT (system ) 1 VREF tIS tIH CKE LVCMOS LOW LEVEL ( ( ) ) t IS tIH ( ( ) ) ...

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... IS43R83200D IS43/46R16160D, IS43/46R32800D MODE REGISTER (MR) DEFINITION  The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the definition of a burst length, a burst type, and a CAS latency. The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is reprogrammed, or the device loses power. Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave), A4-A6 the CAS latency, and A8 DLL reset. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility. The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation ...

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... IS43R83200D IS43/46R16160D, IS43/46R32800D BURST LENGTH Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being set and the burst order as in Burst Definition. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types. BURST DEFINITION   Burst  Starting Column Address Length ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-An when the burst length is set to two, by A2-An when the burst length is set A3-An when the burst length is set the most significant column address bit, which depends if the device is x8, x16 or x32 for x8 for x16 and for x32. The programmed burst length applies to both read and write bursts. BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. READ LATENCY The READ latency, or CAS latency, is the delay between the registration of a READ command and the availability of the first piece of output data READ command is registered at a clock edge n and the latency is 3 clocks, the first data element will be valid 2tCK + tAC READ command is registered at a clock edge n and the latency is 2 clocks, the first data element will be valid tCK + tAC. OPERATING MODE The normal operating mode is selected by issuing a Mode Register Set command with bits each set to zero, and bits set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and each set to zero, bit A8 set to one, and bits set to the desired values. A Mode Register Set command issued to reset the DLL must always be followed by a Mode Register Set command to select normal operating mode (A8=0). All other combinations of values for are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 17 ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D 18 CAS LATENCIES Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 ...

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... DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled a DLL Reset must follow and 200 clock cycles must occur before any executable command can be issued. OUTPUT DRIVE STRENGTH (DS) The normal drive strength for all outputs is specified to be SSTL_2, Class II. This DRAM also supports a reduced driver strength option, intended for lighter load and/or point-to-point environments. EXTENDED MODE REGISTER BA1 BA0 A12 A11 A10 ...

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... IS43R83200D IS43/46R16160D, IS43/46R32800D Absolute Maximum Rating Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability AC/DC Electrical Characteristics and Operating Conditions Recommended operating conditions (Voltage referenced to VSS=0V +105 o C for A2) Parameter Supply voltage (with a nominal VDD of 2 ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D CAPACITANCE CHARACTERISTICS ( 2.5V + 0.2V, unless otherwise noted) DD DDq Symbol Parameter CI(A) Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CLK pin CI/O I/O Capacitance, I/O, DQS, DM pin Notes: 1. This parameter is characterized. 2. Conditions: Frequency = 100MHz; V THERMAL RESISTANCE Package Substrate TSOP2(66) 4-layer BGA(60) 4-layer BGA(144) 4-layer Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 (1, 2) Test Condition ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D IDD Specification Parameters and Test Conditions: x8, x16 ( 2.5V ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted) DD DDq Symbol Parameter/ Test Condition IDD0 Operating current for one bank active-precharge; tRC = tRC(min); tCK = tCK(min); DQ, DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles high between valid commands. IDD1 Operating current for one bank operation; one bank open tRC = tRC(min), tCK = tCK(min), Iout=0mA, Address and control inputs changing once per clock cycle. IDD2P Precharge power-down standby current; all banks idle; power-down mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and DM IDD2F Precharge floating standby current; CS VIH(min); all banks idle; CKE VIH(min); tCK = tCK(min); address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM IDD3P Active power-down standby current; one bank active; power-down mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and DM IDD3N Active standby current; CS VIH(min); CKE VIH(min); one bank active; tRC = tRAS(max); tCK = tCK(min); DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD4R Operating current for burst read; burst length = 2; reads; continuous burst; one bank active; address and control inputs changing once per ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D IDD Specification Parameters and Test Conditions: x32 ( 2.5V ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted) DD DDq Symbol Parameter/ Test Condition IDD0 Operating current for one bank active-precharge; tRC = tRC(min); tCK = tCK(min); DQ, DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles high between valid commands. IDD1 Operating current for one bank operation; one bank open tRC = tRC(min), tCK = tCK(min), Iout=0mA, Address and control inputs changing once per clock cycle. IDD2P Precharge power-down standby current; all banks idle; power-down mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and DM IDD2F Precharge floating standby current; CS VIH(min); all banks idle; CKE VIH(min); tCK = tCK(min); address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM IDD3P Active power-down standby current; one bank active; power-down mode; CKE VIL(max); tCK = tCK(min); VIN = VREF for DQ, DQS and DM IDD3N Active standby current; CS VIH(min); CKE VIH(min); one bank active; tRC = tRAS(max); tCK = tCK(min); DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle IDD4R Operating current for burst read; burst length = 2; reads; continuous burst; one bank active; address and control inputs changing once per ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D AC TIMING REQUIREMENTS Absolute Specifications (VDD, VDDQ = +2.5 V ±0.2 V) PARAMETER DQ output access time for CLK,/CLK DQS output access time for CLK,/CLK CLK high-level width CLK low-level width CLK half period CLK cycle time CL=3 CL=2.5 CL=2 DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width (for each input) DQ and DM input pulse width (for each input) DQ & DQS high-impedance time from CLK,/CLK DQ & DQS low--impedance time from CLK,/CLK DQS--DQ Skew, DQS to last DQ valid, per group, per access DQ/DQS output hold time from DQS Data Hold Skew Factor Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CLK setup time DQS falling edge hold time from CLK MODE REGISTER SET command cycle time Write preamble setup time Write postamble Write preamble Address and Control input hold time (fast slew rate) Address and Control input setup time (fast slew rate) Address and Control input hold time (slow slew rate) ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D AC TIMING REQUIREMENTS Absolute Specifications (VDD, VDDQ = +2.5 V ±0.2 V@-5/-6) PARAMETER ACTIVE to ACTIVE/Auto Refresh command period Auto Refresh to Active/Auto ACTIVE to READ or WRITE delay PRECHARGE command period Active to Autoprecharge Delay ACTIVE bank A to ACTIVE bank B command Write recovery time Auto Precharge write recovery + precharge time Internal Write to Read Command Delay Exit self refresh to non-READ Exit self refresh to READ command Average Periodic Refresh Interval (x8/x16) Average Periodic Refresh Interval (x32) Output Load Condition REF Ω OUT Ω Zo=50 30pF Integrated Silicon Solution, Inc. Rev.  B ...

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... edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW previous write was in prog- ress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode. 19. For command/address and CK & /CK slew rate > 1.0V/ns. 20. Min (tCL,tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device. ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D OUTPUT SLEW RATE CHARACTERISTICS Slew Rate Characteristic Typical Range  Pullup Slew Rate 1.2-2.5 Pulldown Slew Rate 1.2-2.5 AC OVERSHOOT/UNDERSHOOT SPECIFICATION FOR ADDRESS AND CONTROL PINS Parameter Peak amplitude allowed for overshoot Peak amplitude allowed for undershoot Area between the overshoot signal and VDD must be less than or equal to (see figure below) Area between the undershoot signal and GND must be less than or equal to (see figure below Volts +1 ( Address and Control AC Overshoot and Undershoot Definition OVERSHOOT/UNDERSHOOT SPECIFICATION FOR DATA, STROBE, AND MASK PINS Parameter Peak amplitude allowed for overshoot Peak amplitude allowed for undershoot Area between the overshoot signal and VDD must be less than or equal to (see figure below) Area between the undershoot signal and GND must be less than or equal to (see figure below Volts +1 ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D 32Mx8 ORDERING INFORMATION - VDD = 2.5V Commercial Range: 0°C to +70°C   Frequency  Speed (ns)   Order Part No.  200 MHz 5 IS43R83200D-5TL 166 MHz 6 IS43R83200D-6TL Industrial Range: -40°C to +85°C   Frequency  Speed (ns)   Order Part No.  200 MHz 5 IS43R83200D-5TLI 166 MHz 6 IS43R83200D-6TLI 28 Package 66-pin TSOP-II, Lead-free 66-pin TSOP-II, Lead-free Package 66-pin TSOP-II, Lead-free 66-pin TSOP-II, Lead-free Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 ...

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... IS46R16160D-6TLA1 Automotive (A2) Range: -40°C to +105°C   Frequency  Speed (ns)   Order Part No.  166 MHz 6 IS46R16160D-6BLA2 IS46R16160D-6TLA2 8Mx32 ORDERING INFORMATION - VDD = 2.5V Commercial Range: 0°C to +70°C   Frequency  Speed (ns)   ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D 30 Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D Mini Ball Grid Array Package Code: B (60-Ball) 8mm x 13mm Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 31 ...

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IS43R83200D IS43/46R16160D, IS43/46R32800D 32 Integrated Silicon Solution, Inc. Rev.  B 06/19/2012 ...