IDT74SSTUBF32866BBFG IDT, Integrated Device Technology Inc, IDT74SSTUBF32866BBFG Datasheet - Page 17
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IDT74SSTUBF32866BBFG
Manufacturer Part Number
IDT74SSTUBF32866BBFG
Description
IC BUFFER 25BIT REG DDR2 96-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT74SSTUBF32866BBFG.pdf
(30 pages)
Specifications of IDT74SSTUBF32866BBFG
Logic Type
1:1, 1:2 Configurable Registered Buffer
Supply Voltage
1.7 V ~ 1.9 V
Number Of Bits
25, 14
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
96-BGA
Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
410(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74SSTUBF32866BBFG
800-1695
800-1695
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT74SSTUBF32866BBFG
Manufacturer:
HBa
Quantity:
826
Company:
Part Number:
IDT74SSTUBF32866BBFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT74SSTUBF32866BBFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Register Timing
NOTES:
1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of t
error.
2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
D1 - D25
Q1 - Q25
RESET
PARIN
QERR
Timing Diagram for SSTUBF32866B Used as a Single Device; C0 = 0, C1 = 0, RESET Switches from L to H
DCS
CSR
PPO
CLK
CLK
(1)
(1)
(2)
t
ACT
H, L, or X
n
t
SU
t
PDM,
CLK to Q
t
PDMSS
Data to QERR Latency
n +1
t
SU
CLK to QERR
17
t
H
t
PHL
n + 2
CLK to PPO
t
H
t
PD
COMMERCIAL TEMPERATURE GRADE
n + 3
H or L
CLK to QERR
t
PHL,
IDT74SSTUBF32866B
t
PLH
n + 4
ACTMAX
, to avoid false
7067/13