853S024AYLFT IDT, 853S024AYLFT Datasheet

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853S024AYLFT

Manufacturer Part Number
853S024AYLFT
Description
Clock Drivers & Distribution
Manufacturer
IDT
Datasheet

Specifications of 853S024AYLFT

Rohs
yes
Part # Aliases
ICS853S024AYLFT
General Description
The ICS853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V
LVPECL Fanout Buffer. The PCLK, nPCLK pair can accept most
standard differential input levels. The ICS853S024 is characterized
to operate from either a 3.3V or a 2.5V power supply. Guaranteed
output skew characteristics make the ICS853S024 ideal for those
clock distribution applications demanding well defined performance
and repeatability.
Block Diagram
nPCLK
ICS853S024AY REVISION A JULY 20, 2011
PCLK
Pulldown
Pullup/Pulldown
Low Skew, 1-to-24, Differential-to-3.3V, 2.5V
LVPECL Fanout Buffer
24
24
Q[0:23]
nQ[0:23]
1
Features
nQ0
nQ2
nQ1
nQ3
nQ4
nQ5
Pin Assignment
V
V
V
V
Q0
Q1
Q2
Q3
Q5
Q4
CC
EE
CC
EE
Twenty four LVPECL outputs.
One differential clock input pair
Differential input clock (PCLK, nPCLK) can accept the following
signaling levels: LVDS, LVPECL, CML
Maximum output frequency: 2GHz
Translates any single ended input signal to 3.3V, 2.5V LVPECL
levels with resistor bias on nPCLK input
Output skew: 125ps (maximum)
Rise and Fall Time: 180ps (typical)
Additive phase jitter, RMS: 0.15ps (typical) @ 156.25MHz
Full 3.3V or 2.5V supply voltage
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
1
2
3
4
5
6
8
10
11
12
13
14
15
16
7
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
10mm x 10mm x 1mm
64-Lead TQFP, EPad
package body
ICS853S024
Y Package
Top View
©2011 Integrated Device Technology, Inc.
ICS853S024
41
38
48
47
46
45
44
43
42
40
39
37
36
35
34
33
DATA SHEET
nPCLK
PCLK
nQ17
Q17
nQ16
Q16
nQ15
Q15
nQ14
Q14
nQ13
Q13
nQ12
Q12
V
V
CC
CC

Related parts for 853S024AYLFT

853S024AYLFT Summary of contents

Page 1

Low Skew, 1-to-24, Differential-to-3.3V, 2.5V LVPECL Fanout Buffer General Description The ICS853S024 is a low skew, 1-to-24 Differential-to-3.3V, 2.5V LVPECL Fanout Buffer. The PCLK, nPCLK pair can accept most standard differential input levels. The ICS853S024 is characterized to operate from ...

Page 2

ICS853S024 Data Sheet Table 1. Pin Descriptions Number Name 1, 16, 18, 31 33, 34, 50, 63 15, 17, 32 Q0, nQ0 5, 6 Q1, nQ1 7, 8 Q2, nQ2 9, ...

Page 3

ICS853S024 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 4

ICS853S024 Data Sheet Table 3D. LVPECL DC Characteristics, V Symbol Parameter V Output High Voltage; NOTE Output Low Voltage; NOTE Peak-to-Peak Output Voltage Swing SWING NOTE 1: All outputs are terminated with 50Ω to ...

Page 5

ICS853S024 Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase ...

Page 6

ICS853S024 Data Sheet Parameter Measurement Information LVPECL V EE -1.3V±0.165V 3.3V LVPECL Output Load AC Test Circuit V CC nPCLK V Cross Points PP PCLK V EE Differential Input Level Par t 1 nQx Qx Par t ...

Page 7

... PERIOD t PW odc = t PERIOD Output Duty Cycle/Pulse Width/Period Applications Information Recommendations for Unused Output Pins Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. All supplies must be connected ...

Page 8

ICS853S024 Data Sheet Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage V the bias resistors R1 and R2. The bypass capacitor (C1) ...

Page 9

ICS853S024 Data Sheet 3.3V LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS, CML and other differential signals. Both V and V SWING V input requirements. Figures show interface examples CMR for the PCLK/ nPCLK input ...

Page 10

ICS853S024 Data Sheet 2.5V LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS, CML and other differential signals. Both V and V SWING V input requirements. Figures show interface examples CMR for the PCLK/ nPCLK input ...

Page 11

ICS853S024 Data Sheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that ...

Page 12

ICS853S024 Data Sheet Termination for 2.5V LVPECL Outputs Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω – 2V. For V = 2.5V, the ...

Page 13

ICS853S024 Data Sheet EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the ...

Page 14

ICS853S024 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS853S024. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS853S024 is the sum of the ...

Page 15

ICS853S024 Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure Figure 7. LVPECL ...

Page 16

ICS853S024 Data Sheet Reliability Information θ Table 6. vs. Air Flow Table for a 64 Lead TQFP, E-Pad JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS853S024 is: 8336 ICS853S024AY REVISION A ...

Page 17

ICS853S024 Data Sheet Package Outline and Package Dimensions Package Outline - Y Suffix for 64 Lead TQFP, E-Pad Table 7. Package Dimensions for 64 Lead TQFP, E-Pad JEDEC Variation: ACD All Dimensions in Millimeters Symbol Minimum Nominal ...

Page 18

... Marking 853S024AYLF ICS853S024AYLF 853S024AYLFT ICS853S024AYLF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 19

... IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT ...

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