K6X0808C1D-BF55000 Samsung, K6X0808C1D-BF55000 Datasheet - Page 7

• Manufacturer Part Number: K6X0808C1D-BF55000
• Description: power, ram, low, Memory, Semiconductors and Actives, bit, cmos
• Manufacturer: Samsung

K6X0808C1D Family
DATA RETENTION WAVE FORM
CS controlled
TIMING WAVEFORM OF WRITE CYCLE(2)
TIMING WAVEFORM OF WRITE CYCLE(1)
Address
CS
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
2. t
3. t
4. t
V
4.5V
2.2V
V
CS
GND
Address
CS
WE
Data in
Data out
CC
DR
going low : A write end at the earliest transition among CS going high and WE going high, t
to the end of write.
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the CS going low to the end of write.
is measured from the end or write to the address change. t
Data Undefined
High-Z
t
SDR
t
t
AS(3)
AS(3)
(CS Controlled)
(WE Controlled)
7
WR
Data Retention Mode
t
WHZ
t
AW
applied in case a write ends as CS or WE going high.
t
CS≥V
AW
t
t
WC
CW(2)
t
CW(2)
t
WC
t
CC
t
WP(1)
WP(1)
- 0.2V
t
t
DW
DW
Data Valid
Data Valid
WP
is measured from the begining of write
t
t
WR(4)
WR(4)
t
t
DH
DH
t
OW
CMOS SRAM
High-Z
t
RDR
Revision 3.0
March 2005