DM9010_06 DAVICOM [Davicom Semiconductor, Inc.], DM9010_06 Datasheet - Page 25

• Manufacturer Part Number: DM9010_06
• Description: 10/100 Mbps Single Chip Ethernet Controller with General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.29 Transmit Check Sum Control Register ( 31H )
6.30 Receive Check Sum Control Status Register ( 32H )
6.31 External PHYceiver Address Register ( 33H )
6.32 General Purpose Control Register 2 ( 34H )
Preliminary
Version: DM9010-17--DS-P04
Jan. 18, 2006
1~0
7~3
6~5
4~0
Bit
Bit
Bit
Bit
2
1
0
7
6
5
4
3
2
1
0
7
RESERVED
EPHYADR
UDPCSE
Reserved
TCPCSE
ADR_EN
RCSEN
IPCSE
Name
Name
UDPS
UDPP
DCSE
Name
Name
TCPS
TCPP
ETT
IPS
IPP
HPS0,RO UDP CheckSum Status
HPS0,RO TCP CheckSum Status
HPS0,RO IP CheckSum Status
HPS0,RO UDP Packet
HPS0,RO TCP Packet
HPS0,RO IP Packet
HPS0,RO Reserved
HPS01,R
HPS0,RW
HPS0,RW
HPS0,RW
HPS0,RW
HPS0,R
HPS0,R
HPS0,R
Default
Default
Default
Default
0,RO
W
W
W
W
0: checksum OK, if UDP packet
0: checksum OK, if TCP packet
0: checksum OK, if IP packet
Receive CheckSum Checking Enable
When set, the checksum status will store in packet first byte of status header.
Discard CheckSum Error Packet
When set, if IP/TCP/UDP checksum field is error, this packet will be discarded.
External PHY Address Enabled
When set in external MII mode, the external PHYceiver address is defined at bit
4~0.
External PHY Address Bit 4~0
The PHY address in external MII mode.
Early Transmit Threshold
Start transmit when data write to TX FIFO reach the byte-count threshold
Bit-1 bit-0
----- ----
0
0
1
1
Reserved
UDP CheckSum Generation Enable
TCP CheckSum Generation Enable
IP CheckSum Generation Enable
Single Chip Ethernet Controller with General Processor Interface
0
1
0
1
: 12.5%
: 25%
: 50%
: 75%
threshold
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Description
Description
Description
Description
DM9010
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